Zynq devices are split into two distinct sections: the programmable logic (PL) section and the processing system (PS) section. This blog will predominantly focus on implementing a PS system augmented with a simple logic design within the PL fabric, thereby allowing me to demonstrate an implementation that uses both sections of the Zynq.
The first step in this development is to open PlanAhead and create a new RTL project as shown in the following two images:
This is fairly straightforward since -- as you initially have no existing RTL, IP, or constraints -- you can simply keep on selecting the "Next" option until you reach the "Device Selection" dialog. It is at this dialog that you should select the board option -- not the device -- and target the Xilinx ZC702 Evaluation board as shown below. Yes, I know that this is not the ZedBoard, but we will return to deal with this point in my next blog:
Once the project has been created, you will be presented with the default screen in PlanAhead, at which point you need to add a source to the design. You can do this by selecting the "Add Sources" item under the "Project Manager" options in the "Flow Navigator" area, which should be on the left-hand side of the screen as shown below:
As we are currently interested in getting the processing system side of the Zynq up and running, select the "Add or Create Embedded Sources” option as shown in the following image. As we shall see, the general-purpose input/output (I/O) for our programmable logic will be called up here as well:
This will open yet another dialog, from which we can select the “Create Sub-Design” button as shown in the image below:
OK, we're almost there. Although this may seem a little complicated, it's actually pretty easy once you get the hang of it. In my next blog we will complete the configuration and use PlanAhead to generate the bitstream and download it into the device. Do you have any questions thus far?