"The most valuable people are the ones who can integrate the most different disciplines." -- J. Thomas Pawlowski
J. Thomas Pawlowski is a fellow and chief technologist with Micron's Architecture Development Group. In this role, he evaluates new technologies and memory architectures. During his career, Pawlowski has helped develop numerous memory architectures and concepts, including synchronous pipelined SRAM, hierarchical cache systems, zero bus turnaround SRAM, the first double-data-rate memory (SRAM, and then DRAM and NAND), PSRAM, high-speed NAND, the first double-address-rate memory, the first quad-data-rate memory, the first multi-channel memory, memories on SERDES buses, and the first DRAM to exceed SRAM performance (RLDRAM).
Trained in electrical engineering at the University of Waterloo in Canada, Pawlowski holds approximately 150 US and international patents and serves on several advisory boards. He will be a keynote speaker at the upcoming DesignCon in Santa Clara, Calif., speaking on Thursday, January 30, 2014 from 12:00 p.m. to 12:30 p.m. PST in the Mission City Ballroom of the Santa Clara Convention Center. I thought it might be nice to get to know him a bit beforehand, and so I asked him to participate in our Profiles in Design series.
EDN: Why did you first get into this area/career?
TP: I chose moving into the area of memory technology and architecture way back in 1992, because it appeared to be the area that was in need of the most improvement.
EDN: What do you find fascinating about engineering?
TP: I love the combination of creativity and free thinking combined with the urgent problems that need solutions. What a privilege it is to do something so meaningful and be paid to have this much fun.
Read the full article on EDN.com.
— Janine Love , UBM Tech