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CeRAM Memory Gets ARM's Attention
2/6/2014

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Figure 2
(a) Plot of CeRAM switching characteristics on log scale.
(b) Linear scanof CeRAM I-V characteristics.(Source: Chris McWilliams)
(a) Plot of CeRAM switching characteristics on log scale. (b) Linear scan
of CeRAM I-V characteristics.
(Source: Chris McWilliams)

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krisi
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congrats
krisi   2/6/2014 4:03:36 PM
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Congrats Carlos, you did it again...would you be interested in presenting this at emerging technologies symposium in Vancouver in 2015? preliminary program at www.cmosetr.com, cheers, Kris (kris.iniewski@gmail.com)

nonvolatile
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Re: congrats
nonvolatile   2/6/2014 4:36:47 PM
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Yes - send me an email. I was a little busy last time. Thanks for your unending support.

krisi
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Re: congrats
krisi   2/6/2014 4:45:19 PM
thank you Carlos, will do...if anyone else is interested pls drop me an email, we will be orgazining in Vancouver in 2015 with Santosh Kurinec a session on emerging memories...BTW, our book on this topic is out: http://www.amazon.ca/Nanoscale-Semiconductor-Memories-Technology-Applications/dp/1466560606...conference link is www.cmosetr.com, Kris

resistion
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compliance
resistion   2/7/2014 12:15:09 AM
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If it needs compliance, it's filamentary, I'm afraid.

Ron Neale
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Re: compliance
Ron Neale   2/7/2014 5:51:39 AM
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Resistion: I think the validity of your point, filament versus bulk switching, would rest with you providing our readers with an explanation of the mechanism that allows the formation of  an insulating filament in a material that it is claimed is highly conducting in its as-born state. If you consider a planar parallel electrode structure once your insulating filament is formed why would the material surrounding your filament that is still in its conducting state and subjected to the same applied voltage not switch to the insulating state? The claimed lack of a need for forming is a key point. 

resistion
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Re: compliance
resistion   2/7/2014 6:18:07 AM
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The key is without compliance what happens.

alex_m1
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Re: compliance
alex_m1   2/7/2014 6:52:15 AM
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How soon are we going to see it in products ?

nonvolatile
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Re: compliance
nonvolatile   2/7/2014 8:13:32 AM
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Compliance - we spent over 5 years gettting rid of the bugs. So, we are entering now a development stage - as you may know, in industrial research we have first a prove of concept and then R&D to show that it is real and useful. After that there is an engineering benchmarking phase, the develpment phase, in which design and processes cand comply with product specs and reliability. We are at this point. The teams separate - one continues further R&D for other applications and the technology team does the Test Chips at a given node, Typically this is about 2 years. We are entering that curve now. So 2 years is a good number. The nice thing here is that this is fab compatible and we do not need Platinum electrodes as the otherRRAMs usually do.

alex_m1
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Re: compliance
alex_m1   2/7/2014 10:15:16 AM
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Since you're fab compatible, in 2 years we'll see memories or also SOC's/microcontrollers intergarting CeRAM ?

nonvolatile
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Re: compliance
nonvolatile   2/7/2014 10:31:26 AM
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I hope so. Maybe sooner.

resistion
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Re: compliance
resistion   2/7/2014 11:02:30 AM
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Hope to see some array demos if you can get to publish those results..

nonvolatile
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Re: compliance
nonvolatile   2/7/2014 11:19:52 AM
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ok-soon

resistion
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Re: compliance
resistion   2/7/2014 7:33:13 AM
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What is the perceived difficulty for forming? Wouldn't it be a negligible part of testing anyway?

nonvolatile
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Re: compliance
nonvolatile   2/7/2014 7:45:29 AM
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Compliance- please read post I just made to resistion and ask yourself if frying a device with higher voltage and high current to form random filament creation is good in say a 10 nm technological Node. A bad start in making so that you have rsistance switching.

resistion
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Re: forming
resistion   2/7/2014 8:22:54 AM
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My understanding is the initial state for resistive memory determines the initial operation. For an insulator like HfO2, there would be an initial step similar to breakdown, but not as drastic as in antifuse OTP. For an initially conducting state, the initial operation would be the RESET, which should be very high current for something metallic. 

nonvolatile
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Re: forming
nonvolatile   2/7/2014 8:34:47 AM
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I think that you meant Vset, as in these cases, the forming voltage is of the same order as the set voltage. These arguments of "No forming needed" have entered the arena recently, specially in HfO. But, they do not mean that no filaments are made. And, again, it is a matter of reliability. How reliable is the "disconnect" region of these filaments. Can one really bank on random electrochemical reactions for a memory. Some will say that certain tailoring of the filament map etc. can eventually make a good memory device. I heard a lot about this kind of argument when we were in the Phase Change Memory area. I do not believe that strucutral thermally driven phase transitions are an answer to 10 nm devices and beyond. We have to have something better - something truly quantum and not metallurgical.

resistion
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Re: forming
resistion   2/7/2014 8:49:54 AM
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Yes, I agree a filamentary forming-free device is still filamentary. Recently, there have been pictures of filamentary structures (mostly TaOx-based) and unexpectedly there wasn't a single dominant one, but it looked like many at the interface. Sometimes it is reported the filament is like a metal, sometimes like a semiconductor. I sometimes wonder if the filament is going through the metal-insulator transition. And with many filaments occurring, where to draw the line separating from area-based...even Schottky and STT can be non-uniform.

nonvolatile
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Re: forming
nonvolatile   2/7/2014 9:02:47 AM
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Right on. It is not an easy task to discriminate what is the dominant phase transition mechanism in the reative region of where the filament is. The Schottky barrier is a space charge region which is not ever a constant potential area - in fact it goes from a high field to the zero field point wher the space charge is fully compensated by the bulk charge, In fact all semiconductor devices dependend on pn,Schottky and MOs space charge regions - all call this the 5 Schikley equations and 3 regions devices. The field distribution and the cyrstal field plus defects are a deadly mix for a stable memory device. And, since there is no hysterectic behavior intrnisic to semiconductors, we have to live with oxides and the like to make nonvolatile memories (where hysteresis is a must). Now in FLASH you have charge trapping in the floating gate causing threshold voltage hysteresis. We know that that is not a great solution in terms of endurance and power. Now, shemes  as you describe that technically end up in charge trapping are not of potentially great future either, as eventually reliability lomits in controlling the traps squeeze you in. So, when we saw the universality of CeRAM being a quantum phenomenon that is not dependent in single crystals and right off the bat it shows easy integration and fulfills a cost/performance market node, you can imagine our excitement. But to tell you the truth, the academic side of me, specially in device physics, is what really turn me on. 

Ron Neale
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Re: compliance
Ron Neale   2/7/2014 8:28:14 AM
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Resistion; The need for forming brings with it at least at two problems and maybe more. If forming requires conditions different normal operation then that adds a burden to the initial user of the as-born device or as you suggest the test budget. In that it is first necessary to apply a forming cycle to every cell prior to testing. This would not be negligible as you suggest for a 16Gbit device. The second consideration is relaibility, does a device in its just formed state have the same level of reliability as a device in its F+1 write/erase cycle state.

Example: Long ago in the early days of Phase Change Memory (PCM) if the devices were made in the amorphous state then sometimes the natural annealing of the amorphous material in its as deposited state would cause the threshold voltage to drift above the value at which the array could be operated. With very small arrays the techique we used was to thermally crystallize the material during fabrication then at the test stage run multiple reset pulses, to erase all of the active material in each pore, then test. Not something I would recommend for 16Gbits. The later introduction of the edge contact (dome/mushroom) PCM solved that problem to a degree and allowed PCMs to be fabricated in the crystal conducting as-born state; even so the initial pulse is still a dome forming pulse. 

resistion
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Re: forming-free
resistion   2/7/2014 8:41:47 AM
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There have been many examples of forming-free resistive memories. In the ideal case, the RESET state is virtually the same as the initial. But I haven't surveyed this extensively in a while, so I can't comment how common this is.

nonvolatile
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Re: compliance
nonvolatile   2/7/2014 6:40:20 AM
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Unfortunately this is not true. Compliance simply limits the amount of current and has nothing to do with whether a filament is present or not. If the bulk switches to a conducting state, the current will flow like in a metal. It will increase with the ability of the metal to pass more current. But, once the voltage/current goes to zero, there is no more current. Now, as you re-start from zero upt to the turn-off voltage, the mechanism to turn off the current means that something inside the material is able to stop flow of carriers. That something when there is a filament, would be some kind of filament break or disconnect reaction. What kind of reaction? in these transition metal oxides, the first thing that comes to mind is a change in oxidation number that would create some distortion in the local fields. and, in many cases, this is what happens to filaments near the anode. The anode can source electrons or holes, but mostly there will be a deficit of electrons a few lattice constants under the anode, just enough to break a filament. In our case, this random breaking of filaments by an electrochemical reaction is taken out of the equation by providing a highly conductive doped layr of NiO. Then, in a very thin middle layer, only about20 atoms thick, the active switching region is built. Enough analysis with XPS etc. has shown that this switched region is uniform and has different dominance of oxidation numbers of the right kind (+1,+3,+2) and none of the filament kind in the conductive state or otherwise(+0, metallic NiO). So, not only there is physical evidence from the spectroscopic data, but also from the electrical data, as hole injection from the anode controls the shut-off, Now, the step of making it conductive, with the compliance, is proportional to this hole current that appears going from zero volts to Vreset (turn off voltage). Experiments can be designed to literaly control how many electrons you want to come in at the seting voltage, and how many holes to come in to turn it off. That is, you must "erase" the amount of excess electrons that created the conductive state with incoming holes. This can be very precise and vary with doping levels to the point that the maximum "ON" current in the ohmic side of the IV curve, at a maximum, will be exactly the value of the compliance current. None of this could happen with any kind of filament through the perfectly metallic constituint Ni(0+).  And, if the buffer layer, which is conductive, was made up of filaments, it would extinguish holes right away and never get to the thin middle layer of 20 atoms thick. And, if the thin layer would be of filaments, it would never be under the metal/insulator interface near the anode to have a disconnect reaction. This and many other considerations of what kind of potential energy landscape the Ni ion sees with or without doping, make it almost indisputable the filament argument in CeRAM.

 

resistion
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Re: compliance
resistion   2/7/2014 7:19:48 AM
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Per your paper J. Appl. Phys. 109, 091603 (2011), your CeRAM film is polycrystalline, so should have grain boundaries, which are defects that naturally lead to filament locations.

nonvolatile
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Re: compliance
nonvolatile   2/7/2014 7:56:13 AM
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Yes. True. But counter doping these GBs - like grain boundary decoration is  a way to eliminate that. So, if you read the large post I just made to resistion, you will appreciate that the story is a bit more complex than accidental microstructure mishaps. The conduct/insulate switch is at the heart of this, not whether there is or not a filament. Even with a filament, what makes it become insulating....it is not reasonable to believe that a metal streak can become an insulator, So, as you will read, it is an insulator that can become a metal-like material and never a metal that can become an insulator. So, filament termination is where the locus of an Insulator to metal transition can occur. Better than to lose the need of making a filament all together and prepare the material to naturally go through a MIT as prdicted by quantum theory (Hubbard Hamiltonian). So, polycrystallinity is not an issue here because we do not need electronic states that are "extended" like in semiconductors (and metals), but only a locallised electron-electron strong correlation as described in the other post. I know, it is weird, but physics is better than metaphysics. And, quantum phenomena cannot be described by classical pictures.

resistion
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NiO RRAM
resistion   2/7/2014 12:33:35 AM
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NiO RRAM also has been demonstrated many times. This looks like a doped formulation.

nonvolatile
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Re: NiO RRAM
nonvolatile   2/7/2014 7:42:39 AM
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Resistion - we should analyse what doping really means: in semiconductors, doping is only about 1% at the most. So, you are right, we are cahnging the material with higher than 5% doping levels. But, the doping in semiconductors is to produce in the lattice, places wher (for example) Phosphorus, which is group five, would covalently bind with Silicon (group IV), and have an extra electron without a bond. Then ta the room temperature, that electron is free to move in what we call conduction band. This thermal activation is key, as phophorus now is ionized (Ndonnor is positive). We then can accelerate that electron by applying a field and thus we have n-type conduction in Si. Here, we have a different scenario for the effect of doping. Nickel has incomplete 3d shell, it is like many other transition metals, a case where the 3d shell has less than 10 electrons, does not get filled and already a 4s orbital is created. When bonded with oxygen or another suitable "ligand", these orbitals do not bond nice and covalently with the cation. It is a complex situation depending on hoe the oxygen wraps around the Ni ion. This wraping around is called the coordination number - and how many and what charge arrangement, determines what charge the Ni will be able to be. In the case of NiO, we have Ni(+2) and O(-2). And the wraping around is a perfect octahedron with 6 vertices, each sharing 1/6 of an oxygen atom. In the middle of the octahedron is the Nickel ion. This is in theory. In practice, the oxygen atoms simply are not perfectly counter balacing the Ni "charge". So, if an oxygen atom is not there, the area is uncompensated and the Ni simply emits an electron to ounterbalance it. This happens with any transition metal, as the electrons can hop in and out of available empty states (like in the case of Ni, we have the shell with only 8 electrons, Cobalt only 7, Titanium only 1...etc). This hopping is a form of local trap if the oxygen vacancy is there. And, it can be undone with raising the temperature. In the other hand, if we could keep all Nickel ions at a fixed and suitable oxidation number, that is a suitable coordination with its surrounding of perfect oxygen atom compensation, we could proceed with the quantum rearrahgement of electrons that renders NiO an insulator - and that is fone in two steps in nature: first, spin is maximized by what is called Hund's rule. This makes the electrons in the d8 orbital to split states and be at the maximum same spin direction. Not to violate the Pauli exclusion principle, these two electrons cannot be in the same state of energy. Then, we have other Ni ions with the opposit spin that sees the opportunity to jump to the ion that has an unpaired electron of opposite spin, and then this does happen. The double occupancy of this hybrid state creates a repulsion between these electrons and an energy barrier, purely electrostatic appears which makes the NiO become an insulator even though it has this 3d8 energy configuration (9 and 10 being unfilled states would be a conduction band), In 1937, two dutch physisist showed that the normal Wilson-Bloch Band theory would be violated by transition metal oxides because they technically should be conductors and they are not, Neville Mott took that to heart and explained it many years latter with the argument that I just used. In 1963, in a brillliant series of papers, John Hubbard showed that the electrostatic repulsion is a real thing and was able to show how the metal to insulator transition is controlled by this double occupancy of the hybrid state that came out of the old 3d8. In this scenario, doping takes a very different meaning than in a semiconductor. What we call doping here, is a purposively introduced ligand to take place where the oxygen is gone, There are only a few of these. In the high school chemistry experiments, Cobalt and Nickel compounds show brilliantly vivid different colors when mixed with different levels of amonia. In that case, in a liquid, the amonia is a ligand that whenbound to the transition metal, will form different energy windows (like a local absorption/reflection energy deifference) such that different light frequencies get absorbed or not. This is a result of manipulating the oxidation number or coordination "sphere" around the TMO. In our case, we used CO as the most common and stable ligand in the solid state reaction that the material goes through, and in this way, the coordination of Ni is at the very start kept as +2 and the other quantum arrangements of electrons as described above can proceed naturally. That is, the double occupancy will make the material an insulator and if the potential energy for some reason would change, it would become a conductor. The question is, what changes the potential energy well (its spread due to the net positive charge of the core electron+nucleous). The answer is free electrons surrounding it. As an insulator, the second electron became bound due to the double occupancy. How to make it leave? Here is the elegance of nature which is exploited in CeRAM - Electron injection at Vset increases the electron density up to the point that the reach of the positive ion-core positive potential well is reduced and the bound second electron is released, thus the electrostatic repulsion is gone and the gap is gone, and thus a conductive state appears. So, as you can see, in a very thin film of thickenesses in the order of 69 nanometers and bounded by two metal electrodes, the Schottky barriers of the insulator/electrode and the lattice termination is a plethora of defffects such as oxygen vacancies. This is always the same because thermodynamic equilibrium forces thes defects to always exist. What scientist did up to now, was to form filaments of the metal and bank on a memory effect due to electrochemical reactions that appear due to these random changes in oxidation number near the surface. But here, we fis the coordination sphere and move the electron-electron double occupancy region to a thin area in the middle, So, we have a controlled and reversible electron in - electron out "reaction" in the hybrid orbital ( now 3d9). This is a quantum level switch completely regulated by the electron injection or electron deficit created by the lower voltage hole injection. Without the oxygen vacncy traps and without the gross metallic streak defects caused by filament formation, we have a pure quantum phase transition as demonstrated by switching at 4K, which we show in our web site. The simplicity of the operation and the implication of ultrafast switching is a feast to a Many Body Theorist in physics, Here, perhaps for the first time we have command of the Metal_Insulator transition isolated as if in an active region and controlled by electron screen electron density variation similar to the effect known as Degeberacy pressure. Only as recent as 2012, scientist could show that applied pressure of 2.4 Million Atmospheres could make NiO become a metal. Here we can use the mesoscale of the device (thickness) and inject enough electrons to have a density-pressure equivalent(more on this in coming papers). In conclusion, when the coordination sphere is fixed, the electrostatic potential of double occupancy of electrons is of such a high energy that to undo this we cannot even show at up to 400 C. In the case of a filament memory, already at 200s, the detraping of electrons in oxygen vacancies is destroying the insulating state. So, back to your comment, it is like a New Material, but not really. The NiO is just being corrected to behave as if it was a bulk sample and the electron density limited by the compliance is just right to allow a beautiful quantum switch to come into being which is nonvolatile and robust in storage temperature. We are making this quantum switch not only for memory but also for logic (if possible) as if the quantum phase transition is known to be in the 10s of femtosecond order. Thank you for your interest as always.

 

resistion
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Re: NiO RRAM
resistion   2/7/2014 7:49:13 AM
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Was curious if, along same lines, you would be able to apply the same engineering to TiO, VO, NbO, etc. These are materials which seem to be recalled more familiarly regarding MIT. Thanks again.

nonvolatile
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Re: NiO RRAM
nonvolatile   2/7/2014 8:02:57 AM
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Great question. The answer is yes if we can start with a p-type oxide. This covers than all the perovskites, like SrTiO3 and most d-block and f-block elements that have an oxide. But, HfO, NbO, TaO are not p-type. So, when they make HfO, the filaments are needed and I cannot really tell you what is the detail physics of how these materisl open and close fialments, But, I can tell you that so far, I see only sandwiches of different stoichiometry or even different materials (like Tio/TaOx) in order to make this work, The interface between two non-stoichiometric oxides is a very rich area for new things to happen, even superconducting phases have been detecte, But, as a practical matter, banking on that ina manufacturing process for memory - remember Gbits means 1 billion resistors have to be perfect - is a bit too optimistic.

eebert
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Current density
eebert   2/10/2014 9:06:45 AM
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hello, maybe I miss something but the current densities are very low from the I/V curves shown by the writer, how do you expect to have fast random access times froma memory array with such low currents? thanks

Ron Neale
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Re: Current density
Ron Neale   2/10/2014 10:03:00 AM
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I think CeRAM array fabrication and evaluation is the next step as indicated below.  However, if you are suggesting that in a general sense there is some fundamental limit to array size related to read current, or read current density, or you have some formula that links and limits those variables then please share it with us.

For any of the emerging memory technologies looking to achieve large array bit densities, mimnimizing power requires finding the lowest possible write,erase,read current. In many cases the solution will be in array architecture, layout and sense amplifier design.

eebert
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Re: Current density
eebert   2/10/2014 11:54:50 AM
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In todays high-density array architectures, one of the main issue is about the bitline capacitance. If your read current is too low, you cannot read fast because of the bitline load. Of course you can split arrays and multiply sense banks like some already do, but this is a penalty some cannot afford in term of area. Today, I see nobody reading at 1µA or below in standard embedded nvm macrocells e.g., whatever the sense amp. So when I see the IV curves where Itrans=300nA for a 100x100nm square device, I am a bit 'scared'.

nonvolatile
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Re: Current density
nonvolatile   2/11/2014 4:44:04 PM
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Do not be scared. The data that you saw was purposely created for large geometries, with the piurpose of keeping the current low in that application arena. The beauty of CeRAM is that it is uniformily doped, so that the nanoscale devices can still maintain a decent on current that is not too small for bit line capacitance to kill you nor too high such that it is just a dead short. This is done by several means - the CO doping controls the voltage that the device operates, and the "elemental" doping controls the resistance and scattering. So, you can rest easy that the Resistance can be set high enough for a read operation and yet low enough not to make the signal too low.

resistion
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Re: Current density
resistion   2/11/2014 9:21:34 PM
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Yes, and we also have to think about bitline resistance (if it's too long) and transistor channel resistance.

nvdesignth
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Re: Current density
nvdesignth   2/11/2014 9:32:34 PM
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The hard one is to have a working technology. Everything else is just a matter of designing which is exponentially easier.

nonvolatile
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Re: Current density
nonvolatile   2/11/2014 5:32:50 PM
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The key point is the current density that is set by the complience current density equivalent and the materils doping strategy. The data that you see is one that was done for very large areas. It is clear that for very small areas, the resistance can be very high and in the insulating state even higher. This is where the capacitance of the bit line is a major issue, as I believe this is what you are worrying about. Let us now focus on lowering the resistance of the insulating state, as a read pulse would be sent at say 0.2 V. If the resistance is too high, the current is not even measureable. And this would be really a negative point. In essence, this is what led to the "filament" concept. Breaking down most of the small area devices became the normal way to think of RRAMs. And, this led to more than 12 years of research by large companies and laboratories world wide. Samsung for example, had a very definitive paper 12 years ago on NiO, which is still one of the best references. Within the same time period, two initiatives, one in JApan and one in South Korea, created National Centers for correlated electron devices. However, this was a bit too academic. The science was superb but no practical memory device came out. One key point is that there were too many ideas like spintronics, orbitronics and high Tc superconductors. But the idea that correlated electron devices should be the future hit many right notes. Now, a fundamental difference with the CeRAM concept is that the Strong Electron Coreelations are not in the electrons in the "free" electron gas but instead they are in the pairing of electrons in the Nickel Atom. That is, by design a clean (mostly defect free) material - not necessary single crystal, we can control the screening of each Nickel atom (ion) such that, each atom can create the gap or not for insulator to metal transition and vice versa. All p-type insulators can do this and we have made many materials in a controlable way. So, back to your concern, the control of the resistance, specially in the highly insulating state, and get it to work in such a way to have a good "signal" current, is in doping the MIM device. That is, these devices are in essence Metal-Insulator-Metal "diodes" - that is they obey almost perfectly "Simmons Tunneling Formula with Thermionic Emission" However, to make them store in either a conductive state or insulating state, we must either breakdown the oxide and make filaments, or, make a "disproportionation" quantum phase transition - that is, create a gap by spliting an energy level such that the fermi level goes to the middle of the energy gap, or collapsing the gap by screening, and creating a metal like behavior. Contrary to some charge trapping embodiements of RRAM, this is not a field controled device, but a voltage controlled device. The conductivity of the CeRAM devices, when ploting current density vs. electric field, which commonly gives the same slope (conductivity) to any size of area or thickness (standard Ohm's law J=sigma E), it isa completely area dependent. That is, a sigma for every area - clearly not Ohms law. And, you are right, the smallest area gives the smallest sigma. This is a matter of what is called the "Degeneracy Pressure" a purely quantum mechanical phenomenon which has its origin in the Pauli exclusion principle. Well then, the phenomenon is akin to putting actually compressive applied pressure as it is usually done in these insulators. NiO for example, requires 2.4 Million Atmosphere to become a metal. If you look carefully, the relationship between Applied pressure and Degeneracy Pressure is on that leads to Pressure being proportional to electron densities ofraised to 5/3 power. This is acoomplished if we can send by the tunneling at 1.2V (in NiO), electrons equal to this prssure. When this happens, the device conducts and changes the electron density coverage of the Nickel ions creating smaller ion potential radius (goes down to a Bohr radius) in which the bound electron that created the "Gap" and caused the insulating state, to be released. On the other hand, as the anode goes from Zero volts to about 0.6 V (for NiO), the hole injection, for an optimized area to MIM doping ratios, causes the device to go to high resistance as now the electron screening is imperfect. Thus, hole injection is like negative pressure as the electron density goes down near the anode. However, if the device is too small, the volume is small and the lectron Degeneracy Pressure is high, the hole injection is very much constrined by the large electron density. This is the physics of the phenomenon. To understand this well requires that the material is well balanced in maintaining the same coordination number throughout - something that happens only if the stoichiometry is perfect NiO, not NiOx or some dopant that donates electrons and heals the lattice occupying the places where oxygen is lackin. Then comes the first strong answer to your question: Over doping with CO, actually, as simple as puting W(CO)6, a commonly found source for ALD, we can easily go from a complete short to some reasonable resistance value. So, by design - also known as technological control of the material - we can accomplish the reults that are what you wish to see. Also, as you can see in the Symetrix Web site (Symetrixcorp.com) the active region for switching can be as thin as 5-10 nm. So, the thicknesses of near electrode buffer layer, can be thicker, but doped to the point of being shorts. So, imagine that the device is 70 nm thick: the middle layer, 10 nm and the near contact layers are 30 nm. The only thing that makes an insulator happen is the middle layer. The rest of the device is a short. Now, we have the freedom to dope the middle layer too. So, to get the higher current that you are asking for, and lower capacitance, we have 3 degrees of freedom: Thickness of the active region, thickness and doping level of the always conductive buffer layer, and doping of the active region. It is as if we had the ability to dope a filament, control its length and control the distance from filament tio near the electrodes, so that we would control the amount of current passing through the filament. Question - is it not better to control the bulk and not the filament. So, all RRAMs out there, do not have these degress of freedom. Also, because the near electrode material although an oxide, it is always conductive, due to the strong screening caused by the excess electron density due to doping, CeRAMs can have NiSi, COSi and even aluminum as electrodes - NO Platinum is needed, And, since ALD is at about 250 C, there are no temperatures that hurt high node Silicon technology. So, I do not understand why the CBRAM people are so happy with 3 V program and clusters of metal particles randomly moving in a sea of defects is such an answer to the world of Embedded devices. Also, the automotive industry wants higher than 125 C storage. With the quantum effect of CeRAM, it is beyonf further proof that we store both states at 400 c (NiO). Also, reading at 0.2 V has been shown to be stable to 1E12 (as far as we meadured) and that operating temperature varies from 4k (-260 C) to 150 C (as far as we tested) with no problem. So, why is the industry chasing filaments that result from breakdown? Beats me.

nonvolatile
User Rank
CEO
Re: Current density
nonvolatile   2/11/2014 5:44:09 PM
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The key point is the current density that is set by the complience current density equivalent and the materils doping strategy. The data that you see is one that was done for very large areas. It is clear that for very small areas, the resistance can be very high and in the insulating state even higher. This is where the capacitance of the bit line is a major issue, as I believe this is what you are worrying about. Let us now focus on lowering the resistance of the insulating state, as a read pulse would be sent at say 0.2 V. If the resistance is too high, the current is not even measureable. And this would be really a negative point. In essence, this is what led to the "filament" concept. Breaking down most of the small area devices became the normal way to think of RRAMs. And, this led to more than 12 years of research by large companies and laboratories world wide. Samsung for example, had a very definitive paper 12 years ago on NiO, which is still one of the best references. Within the same time period, two initiatives, one in JApan and one in South Korea, created National Centers for correlated electron devices. However, this was a bit too academic. The science was superb but no practical memory device came out. One key point is that there were too many ideas like spintronics, orbitronics and high Tc superconductors. But the idea that correlated electron devices should be the future hit many right notes. Now, a fundamental difference with the CeRAM concept is that the Strong Electron Coreelations are not in the electrons in the "free" electron gas but instead they are in the pairing of electrons in the Nickel Atom. That is, by design a clean (mostly defect free) material - not necessary single crystal, we can control the screening of each Nickel atom (ion) such that, each atom can create the gap or not for insulator to metal transition and vice versa. All p-type insulators can do this and we have made many materials in a controlable way. So, back to your concern, the control of the resistance, specially in the highly insulating state, and get it to work in such a way to have a good "signal" current, is in doping the MIM device. That is, these devices are in essence Metal-Insulator-Metal "diodes" - that is they obey almost perfectly "Simmons Tunneling Formula with Thermionic Emission" However, to make them store in either a conductive state or insulating state, we must either breakdown the oxide and make filaments, or, make a "disproportionation" quantum phase transition - that is, create a gap by spliting an energy level such that the fermi level goes to the middle of the energy gap, or collapsing the gap by screening, and creating a metal like behavior. Contrary to some charge trapping embodiements of RRAM, this is not a field controled device, but a voltage controlled device. The conductivity of the CeRAM devices, when ploting current density vs. electric field, which commonly gives the same slope (conductivity) to any size of area or thickness (standard Ohm's law J=sigma E), it isa completely area dependent. That is, a sigma for every area - clearly not Ohms law. And, you are right, the smallest area gives the smallest sigma. This is a matter of what is called the "Degeneracy Pressure" a purely quantum mechanical phenomenon which has its origin in the Pauli exclusion principle. Well then, the phenomenon is akin to putting actually compressive applied pressure as it is usually done in these insulators. NiO for example, requires 2.4 Million Atmosphere to become a metal. If you look carefully, the relationship between Applied pressure and Degeneracy Pressure is on that leads to Pressure being proportional to electron densities ofraised to 5/3 power. This is acoomplished if we can send by the tunneling at 1.2V (in NiO), electrons equal to this prssure. When this happens, the device conducts and changes the electron density coverage of the Nickel ions creating smaller ion potential radius (goes down to a Bohr radius) in which the bound electron that created the "Gap" and caused the insulating state, to be released. On the other hand, as the anode goes from Zero volts to about 0.6 V (for NiO), the hole injection, for an optimized area to MIM doping ratios, causes the device to go to high resistance as now the electron screening is imperfect. Thus, hole injection is like negative pressure as the electron density goes down near the anode. However, if the device is too small, the volume is small and the lectron Degeneracy Pressure is high, the hole injection is very much constrined by the large electron density. This is the physics of the phenomenon. To understand this well requires that the material is well balanced in maintaining the same coordination number throughout - something that happens only if the stoichiometry is perfect NiO, not NiOx or some dopant that donates electrons and heals the lattice occupying the places where oxygen is lackin. Then comes the first strong answer to your question: Over doping with CO, actually, as simple as puting W(CO)6, a commonly found source for ALD, we can easily go from a complete short to some reasonable resistance value. So, by design - also known as technological control of the material - we can accomplish the reults that are what you wish to see. Also, as you can see in the Symetrix Web site (Symetrixcorp.com) the active region for switching can be as thin as 5-10 nm. So, the thicknesses of near electrode buffer layer, can be thicker, but doped to the point of being shorts. So, imagine that the device is 70 nm thick: the middle layer, 10 nm and the near contact layers are 30 nm. The only thing that makes an insulator happen is the middle layer. The rest of the device is a short. Now, we have the freedom to dope the middle layer too. So, to get the higher current that you are asking for, and lower capacitance, we have 3 degrees of freedom: Thickness of the active region, thickness and doping level of the always conductive buffer layer, and doping of the active region. It is as if we had the ability to dope a filament, control its length and control the distance from filament tio near the electrodes, so that we would control the amount of current passing through the filament. Question - is it not better to control the bulk and not the filament. So, all RRAMs out there, do not have these degress of freedom. Also, because the near electrode material although an oxide, it is always conductive, due to the strong screening caused by the excess electron density due to doping, CeRAMs can have NiSi, COSi and even aluminum as electrodes - NO Platinum is needed, And, since ALD is at about 250 C, there are no temperatures that hurt high node Silicon technology. So, I do not understand why the CBRAM people are so happy with 3 V program and clusters of metal particles randomly moving in a sea of defects is such an answer to the world of Embedded devices. Also, the automotive industry wants higher than 125 C storage. With the quantum effect of CeRAM, it is beyonf further proof that we store both states at 400 c (NiO). Also, reading at 0.2 V has been shown to be stable to 1E12 (as far as we meadured) and that operating temperature varies from 4k (-260 C) to 150 C (as far as we tested) with no problem. So, why is the industry chasing filaments that result from breakdown? Beats me.

nvdesignth
User Rank
Rookie
Congratulations!
nvdesignth   2/11/2014 6:09:51 PM
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Dr. Araujo, CeRAM is looking even better than your successful FeRAM. Wish CeRAM be produced by many foundries so everybody can benefit. Designers are going to have a great time with this CeResistor. It is not going to be used just for a flash replacement. Great work again, congratulations!

 

resistion
User Rank
Manager
Re: Congratulations!
resistion   2/11/2014 9:04:58 PM
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Get in line...behind the other potential flash replacements. :)

resistion
User Rank
Manager
Need for compliance
resistion   2/11/2014 9:29:41 PM
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Looking at the I-V, the CeRAM must have compliance to avoid breakdown (generally a local phenomenon producing a filament). Otherwise it would have self-RESET right after SET, since the SET voltage is larger than RESET voltage.

Ron Neale
User Rank
Blogger
Re: Need for compliance and Oscillations
Ron Neale   2/12/2014 5:36:39 AM
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Resition-Yes without compliance current during the set operation the claimed switching speed combined with the self capacitance would (i = CdV/dt) for large area devices most likely result in destructive currents. And as I think you are suggesting, if the current is not limited then clearly the device would try and RESET itself and it might be considered that a cycle of destructive oscillations would occur. Given the switching speed is a fast as claimed one of the problems of creating a free running oscillators using a simple RC circuit, with a large series resistor from the power supply and a second compliance resistor in series with the capacitor is the need to reduce the voltage to zero after the device is SET.

When a ready supply of CeRAMs becomes available I think one of the projects for the future is to explore the use of the CeRAM as an oscillator, it will be a means of evaluating one aspect of the claimed switching speed. Twice, in the past, I have been involved in exploring the possibility of using threshold switching of phase change materials (PCM) to create a low cost thin film phased array antenna. While free running oscillators could be constructed, one of the problems was it was not possible to get the devices to oscillate a frequencies much above the reciprocal of the thermal time constant; although it was always possible to use the rapid switching transition to ring a microwave cavity and get a burst of pulses, a sort of "chirp".

 

 

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