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Ron Neale
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Re: Need for compliance and Oscillations
Ron Neale   2/12/2014 5:36:39 AM
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Resition-Yes without compliance current during the set operation the claimed switching speed combined with the self capacitance would (i = CdV/dt) for large area devices most likely result in destructive currents. And as I think you are suggesting, if the current is not limited then clearly the device would try and RESET itself and it might be considered that a cycle of destructive oscillations would occur. Given the switching speed is a fast as claimed one of the problems of creating a free running oscillators using a simple RC circuit, with a large series resistor from the power supply and a second compliance resistor in series with the capacitor is the need to reduce the voltage to zero after the device is SET.

When a ready supply of CeRAMs becomes available I think one of the projects for the future is to explore the use of the CeRAM as an oscillator, it will be a means of evaluating one aspect of the claimed switching speed. Twice, in the past, I have been involved in exploring the possibility of using threshold switching of phase change materials (PCM) to create a low cost thin film phased array antenna. While free running oscillators could be constructed, one of the problems was it was not possible to get the devices to oscillate a frequencies much above the reciprocal of the thermal time constant; although it was always possible to use the rapid switching transition to ring a microwave cavity and get a burst of pulses, a sort of "chirp".

 

 

nvdesignth
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Re: Current density
nvdesignth   2/11/2014 9:32:34 PM
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The hard one is to have a working technology. Everything else is just a matter of designing which is exponentially easier.

resistion
User Rank
CEO
Need for compliance
resistion   2/11/2014 9:29:41 PM
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Looking at the I-V, the CeRAM must have compliance to avoid breakdown (generally a local phenomenon producing a filament). Otherwise it would have self-RESET right after SET, since the SET voltage is larger than RESET voltage.

resistion
User Rank
CEO
Re: Current density
resistion   2/11/2014 9:21:34 PM
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Yes, and we also have to think about bitline resistance (if it's too long) and transistor channel resistance.

resistion
User Rank
CEO
Re: Congratulations!
resistion   2/11/2014 9:04:58 PM
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Get in line...behind the other potential flash replacements. :)

nvdesignth
User Rank
Rookie
Congratulations!
nvdesignth   2/11/2014 6:09:51 PM
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Dr. Araujo, CeRAM is looking even better than your successful FeRAM. Wish CeRAM be produced by many foundries so everybody can benefit. Designers are going to have a great time with this CeResistor. It is not going to be used just for a flash replacement. Great work again, congratulations!

 

nonvolatile
User Rank
Rookie
Re: Current density
nonvolatile   2/11/2014 5:44:09 PM
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The key point is the current density that is set by the complience current density equivalent and the materils doping strategy. The data that you see is one that was done for very large areas. It is clear that for very small areas, the resistance can be very high and in the insulating state even higher. This is where the capacitance of the bit line is a major issue, as I believe this is what you are worrying about. Let us now focus on lowering the resistance of the insulating state, as a read pulse would be sent at say 0.2 V. If the resistance is too high, the current is not even measureable. And this would be really a negative point. In essence, this is what led to the "filament" concept. Breaking down most of the small area devices became the normal way to think of RRAMs. And, this led to more than 12 years of research by large companies and laboratories world wide. Samsung for example, had a very definitive paper 12 years ago on NiO, which is still one of the best references. Within the same time period, two initiatives, one in JApan and one in South Korea, created National Centers for correlated electron devices. However, this was a bit too academic. The science was superb but no practical memory device came out. One key point is that there were too many ideas like spintronics, orbitronics and high Tc superconductors. But the idea that correlated electron devices should be the future hit many right notes. Now, a fundamental difference with the CeRAM concept is that the Strong Electron Coreelations are not in the electrons in the "free" electron gas but instead they are in the pairing of electrons in the Nickel Atom. That is, by design a clean (mostly defect free) material - not necessary single crystal, we can control the screening of each Nickel atom (ion) such that, each atom can create the gap or not for insulator to metal transition and vice versa. All p-type insulators can do this and we have made many materials in a controlable way. So, back to your concern, the control of the resistance, specially in the highly insulating state, and get it to work in such a way to have a good "signal" current, is in doping the MIM device. That is, these devices are in essence Metal-Insulator-Metal "diodes" - that is they obey almost perfectly "Simmons Tunneling Formula with Thermionic Emission" However, to make them store in either a conductive state or insulating state, we must either breakdown the oxide and make filaments, or, make a "disproportionation" quantum phase transition - that is, create a gap by spliting an energy level such that the fermi level goes to the middle of the energy gap, or collapsing the gap by screening, and creating a metal like behavior. Contrary to some charge trapping embodiements of RRAM, this is not a field controled device, but a voltage controlled device. The conductivity of the CeRAM devices, when ploting current density vs. electric field, which commonly gives the same slope (conductivity) to any size of area or thickness (standard Ohm's law J=sigma E), it isa completely area dependent. That is, a sigma for every area - clearly not Ohms law. And, you are right, the smallest area gives the smallest sigma. This is a matter of what is called the "Degeneracy Pressure" a purely quantum mechanical phenomenon which has its origin in the Pauli exclusion principle. Well then, the phenomenon is akin to putting actually compressive applied pressure as it is usually done in these insulators. NiO for example, requires 2.4 Million Atmosphere to become a metal. If you look carefully, the relationship between Applied pressure and Degeneracy Pressure is on that leads to Pressure being proportional to electron densities ofraised to 5/3 power. This is acoomplished if we can send by the tunneling at 1.2V (in NiO), electrons equal to this prssure. When this happens, the device conducts and changes the electron density coverage of the Nickel ions creating smaller ion potential radius (goes down to a Bohr radius) in which the bound electron that created the "Gap" and caused the insulating state, to be released. On the other hand, as the anode goes from Zero volts to about 0.6 V (for NiO), the hole injection, for an optimized area to MIM doping ratios, causes the device to go to high resistance as now the electron screening is imperfect. Thus, hole injection is like negative pressure as the electron density goes down near the anode. However, if the device is too small, the volume is small and the lectron Degeneracy Pressure is high, the hole injection is very much constrined by the large electron density. This is the physics of the phenomenon. To understand this well requires that the material is well balanced in maintaining the same coordination number throughout - something that happens only if the stoichiometry is perfect NiO, not NiOx or some dopant that donates electrons and heals the lattice occupying the places where oxygen is lackin. Then comes the first strong answer to your question: Over doping with CO, actually, as simple as puting W(CO)6, a commonly found source for ALD, we can easily go from a complete short to some reasonable resistance value. So, by design - also known as technological control of the material - we can accomplish the reults that are what you wish to see. Also, as you can see in the Symetrix Web site (Symetrixcorp.com) the active region for switching can be as thin as 5-10 nm. So, the thicknesses of near electrode buffer layer, can be thicker, but doped to the point of being shorts. So, imagine that the device is 70 nm thick: the middle layer, 10 nm and the near contact layers are 30 nm. The only thing that makes an insulator happen is the middle layer. The rest of the device is a short. Now, we have the freedom to dope the middle layer too. So, to get the higher current that you are asking for, and lower capacitance, we have 3 degrees of freedom: Thickness of the active region, thickness and doping level of the always conductive buffer layer, and doping of the active region. It is as if we had the ability to dope a filament, control its length and control the distance from filament tio near the electrodes, so that we would control the amount of current passing through the filament. Question - is it not better to control the bulk and not the filament. So, all RRAMs out there, do not have these degress of freedom. Also, because the near electrode material although an oxide, it is always conductive, due to the strong screening caused by the excess electron density due to doping, CeRAMs can have NiSi, COSi and even aluminum as electrodes - NO Platinum is needed, And, since ALD is at about 250 C, there are no temperatures that hurt high node Silicon technology. So, I do not understand why the CBRAM people are so happy with 3 V program and clusters of metal particles randomly moving in a sea of defects is such an answer to the world of Embedded devices. Also, the automotive industry wants higher than 125 C storage. With the quantum effect of CeRAM, it is beyonf further proof that we store both states at 400 c (NiO). Also, reading at 0.2 V has been shown to be stable to 1E12 (as far as we meadured) and that operating temperature varies from 4k (-260 C) to 150 C (as far as we tested) with no problem. So, why is the industry chasing filaments that result from breakdown? Beats me.

nonvolatile
User Rank
Rookie
Re: Current density
nonvolatile   2/11/2014 5:32:50 PM
NO RATINGS
The key point is the current density that is set by the complience current density equivalent and the materils doping strategy. The data that you see is one that was done for very large areas. It is clear that for very small areas, the resistance can be very high and in the insulating state even higher. This is where the capacitance of the bit line is a major issue, as I believe this is what you are worrying about. Let us now focus on lowering the resistance of the insulating state, as a read pulse would be sent at say 0.2 V. If the resistance is too high, the current is not even measureable. And this would be really a negative point. In essence, this is what led to the "filament" concept. Breaking down most of the small area devices became the normal way to think of RRAMs. And, this led to more than 12 years of research by large companies and laboratories world wide. Samsung for example, had a very definitive paper 12 years ago on NiO, which is still one of the best references. Within the same time period, two initiatives, one in JApan and one in South Korea, created National Centers for correlated electron devices. However, this was a bit too academic. The science was superb but no practical memory device came out. One key point is that there were too many ideas like spintronics, orbitronics and high Tc superconductors. But the idea that correlated electron devices should be the future hit many right notes. Now, a fundamental difference with the CeRAM concept is that the Strong Electron Coreelations are not in the electrons in the "free" electron gas but instead they are in the pairing of electrons in the Nickel Atom. That is, by design a clean (mostly defect free) material - not necessary single crystal, we can control the screening of each Nickel atom (ion) such that, each atom can create the gap or not for insulator to metal transition and vice versa. All p-type insulators can do this and we have made many materials in a controlable way. So, back to your concern, the control of the resistance, specially in the highly insulating state, and get it to work in such a way to have a good "signal" current, is in doping the MIM device. That is, these devices are in essence Metal-Insulator-Metal "diodes" - that is they obey almost perfectly "Simmons Tunneling Formula with Thermionic Emission" However, to make them store in either a conductive state or insulating state, we must either breakdown the oxide and make filaments, or, make a "disproportionation" quantum phase transition - that is, create a gap by spliting an energy level such that the fermi level goes to the middle of the energy gap, or collapsing the gap by screening, and creating a metal like behavior. Contrary to some charge trapping embodiements of RRAM, this is not a field controled device, but a voltage controlled device. The conductivity of the CeRAM devices, when ploting current density vs. electric field, which commonly gives the same slope (conductivity) to any size of area or thickness (standard Ohm's law J=sigma E), it isa completely area dependent. That is, a sigma for every area - clearly not Ohms law. And, you are right, the smallest area gives the smallest sigma. This is a matter of what is called the "Degeneracy Pressure" a purely quantum mechanical phenomenon which has its origin in the Pauli exclusion principle. Well then, the phenomenon is akin to putting actually compressive applied pressure as it is usually done in these insulators. NiO for example, requires 2.4 Million Atmosphere to become a metal. If you look carefully, the relationship between Applied pressure and Degeneracy Pressure is on that leads to Pressure being proportional to electron densities ofraised to 5/3 power. This is acoomplished if we can send by the tunneling at 1.2V (in NiO), electrons equal to this prssure. When this happens, the device conducts and changes the electron density coverage of the Nickel ions creating smaller ion potential radius (goes down to a Bohr radius) in which the bound electron that created the "Gap" and caused the insulating state, to be released. On the other hand, as the anode goes from Zero volts to about 0.6 V (for NiO), the hole injection, for an optimized area to MIM doping ratios, causes the device to go to high resistance as now the electron screening is imperfect. Thus, hole injection is like negative pressure as the electron density goes down near the anode. However, if the device is too small, the volume is small and the lectron Degeneracy Pressure is high, the hole injection is very much constrined by the large electron density. This is the physics of the phenomenon. To understand this well requires that the material is well balanced in maintaining the same coordination number throughout - something that happens only if the stoichiometry is perfect NiO, not NiOx or some dopant that donates electrons and heals the lattice occupying the places where oxygen is lackin. Then comes the first strong answer to your question: Over doping with CO, actually, as simple as puting W(CO)6, a commonly found source for ALD, we can easily go from a complete short to some reasonable resistance value. So, by design - also known as technological control of the material - we can accomplish the reults that are what you wish to see. Also, as you can see in the Symetrix Web site (Symetrixcorp.com) the active region for switching can be as thin as 5-10 nm. So, the thicknesses of near electrode buffer layer, can be thicker, but doped to the point of being shorts. So, imagine that the device is 70 nm thick: the middle layer, 10 nm and the near contact layers are 30 nm. The only thing that makes an insulator happen is the middle layer. The rest of the device is a short. Now, we have the freedom to dope the middle layer too. So, to get the higher current that you are asking for, and lower capacitance, we have 3 degrees of freedom: Thickness of the active region, thickness and doping level of the always conductive buffer layer, and doping of the active region. It is as if we had the ability to dope a filament, control its length and control the distance from filament tio near the electrodes, so that we would control the amount of current passing through the filament. Question - is it not better to control the bulk and not the filament. So, all RRAMs out there, do not have these degress of freedom. Also, because the near electrode material although an oxide, it is always conductive, due to the strong screening caused by the excess electron density due to doping, CeRAMs can have NiSi, COSi and even aluminum as electrodes - NO Platinum is needed, And, since ALD is at about 250 C, there are no temperatures that hurt high node Silicon technology. So, I do not understand why the CBRAM people are so happy with 3 V program and clusters of metal particles randomly moving in a sea of defects is such an answer to the world of Embedded devices. Also, the automotive industry wants higher than 125 C storage. With the quantum effect of CeRAM, it is beyonf further proof that we store both states at 400 c (NiO). Also, reading at 0.2 V has been shown to be stable to 1E12 (as far as we meadured) and that operating temperature varies from 4k (-260 C) to 150 C (as far as we tested) with no problem. So, why is the industry chasing filaments that result from breakdown? Beats me.

nonvolatile
User Rank
Rookie
Re: Current density
nonvolatile   2/11/2014 4:44:04 PM
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Do not be scared. The data that you saw was purposely created for large geometries, with the piurpose of keeping the current low in that application arena. The beauty of CeRAM is that it is uniformily doped, so that the nanoscale devices can still maintain a decent on current that is not too small for bit line capacitance to kill you nor too high such that it is just a dead short. This is done by several means - the CO doping controls the voltage that the device operates, and the "elemental" doping controls the resistance and scattering. So, you can rest easy that the Resistance can be set high enough for a read operation and yet low enough not to make the signal too low.

eebert
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Rookie
Re: Current density
eebert   2/10/2014 11:54:50 AM
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In todays high-density array architectures, one of the main issue is about the bitline capacitance. If your read current is too low, you cannot read fast because of the bitline load. Of course you can split arrays and multiply sense banks like some already do, but this is a penalty some cannot afford in term of area. Today, I see nobody reading at 1µA or below in standard embedded nvm macrocells e.g., whatever the sense amp. So when I see the IV curves where Itrans=300nA for a 100x100nm square device, I am a bit 'scared'.

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