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DesignCon Chip Stack Hits 10 TByte/s

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alex_m1
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CEO
Great
alex_m1   2/21/2014 4:45:41 PM
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Really an amazing interface. But this raises questions: considering that   optimized systems which use  cache , run around 10-50 floating point instructions per memory word access. This means that a fitting cpu should run around 100-500 Tera flops per second !


This is clearly impossible with any of today architectures and moore's law current state.

So :what would be a fitting a architecture ? 

HerbR0
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Re: Great
HerbR0   2/23/2014 7:15:24 PM
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Alex, great comment. You are confirming that interposers (2.5D) and vertically stacked dice (3D) are ready to change the system-architecture paradigm. Until now, System Architects are limited by the MEMORY WALL, because current solutions either 1) don't allow to put enough memory into the SoC, right next to the CPU -- because of cost or 2) don't offer sufficient bandwidth or short-enough latency to external memory -- because of power- and cooling constraints.

As your comment highlights, current architectures, if using 2.5D or 3D technology, will run into a CPU WALL and designers can forget about the dreaded memory wall. Highly parallel architectures (I know of a design with a 10,000 bit wide bus) will replace current architectures in high-performance and memory-intensive applications.

Alex, please let me know when and how I may talk to you more about this topic. I am looking for an experienced system designer to convey above benefits clearly and in a compelling way to the system design community -- to trigger new architectures utilizing the 2.5D and 3D-IC strengths. 

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