Today, my topic covers an entirely different type of programmable device, which is referred to as a field-programmable radio frequency (FPRF) chip. But first, let's start with a very quick look at the traditional field-programmable gate array (FPGA) concept.
As we know, FPGAs evolved from simple glue logic consolidation to being capable of implementing complex digital functions. Along the way, they have included a growing range of hard logic cores and functions such as processors and dedicated interface blocks. Some FPGAs also feature sophisticated analog functions such as high speed transceivers, but -- generally speaking -- FPGAs have really only touched the fringes of the analog world.
In contrast, the FPRF comes from the wireless domain and brings exciting new possibilities. At the highest level of abstraction, the FPRF transmitter takes a digital data stream and converts it into wireless signals, while the receiver perform the inverse operation. Add to this the capability to program key parameters like the RF frequency, gain, and bandwidth, and you have the essential ingredients of an FPRF chip as illustrated in the block diagram below:
When I first learned about the device, I could see that it brings similar capabilities for RF to those offered by FPGAs in the logic domain. Firstly, it is programmed by customers, not in the factory. Secondly, the tools allow customers to experiment and change parameters on the fly. Thirdly -- and most importantly -- the applications are limited only by the imagination of the user.
The FPRF chip is fabricated in the US for a UK company called Lime Microsystems. The part number is LMS6002D, but Lime coined the acronym FPRF because it captures the essense of the product.
So let's take a deeper dive into the product. Wireless transmission uses a range of different modulation schemes, and the chip accepts data as In-phase (I Data) and Quadrature (Q Data) words. The transmit path applies the data to a pair of on-chip DACs to convert it into two analog signals. The user can choose to bypass the DACs and inject analog signals directly into the device or monitor the DAC outputs.
The next operation involves filtering the signal. The pass band of this filter is programmed by the user to one of 16 different bandwidths ranging from 1.5 to 28MHz. The filtering restricts the signals to the selected bandwidth, and attenuates any out-of-band noise or aliasing from the DAC. The block diagram for the transmit (TX) path is illustrated in the following diagram:
The filter can boost the signal by 6dB, and is followed by a programmable baseband gain stage that can be adjusted to give up to 31dB of gain in 1dB increments. The signal is then mixed to directly give the required modulated RF frequency output. The TX PLL synthesizer multiplies up the input PLL clock by a programmable ratio, and generates a stable frequency with a tight accuracy. The RF gain stage (programmable, of course) provides the final signal boost that is output from the FPRF device. The transmit power level is sufficient for short range communications, say, tens of meters, without any further amplification. Users can use external amplification to increase the range.
Not surprisingly, the receiver path is also highly programmable. The FPRF device offers a choice of three low noise amplifiers (LNAs). A general broadband input stage is designed to handle RF inputs across the spectrum from 300 MHz to 3.8 GHz. Two further LNAs are optimized for enhanced performance for signals in the range 300 MHz to 2.8 GHz (Lo LNA) and 1.5 to 3.8 GHz (Hi LNA). The block diagram for the receive (RX) path is illustrated in the following diagram:
The mixer in the receive path uses the same PLL clock input as the transmitter, but has a different synthesiser to provide full duplex and direct down conversion. Programmable gain stages and filtering are applied, before the analog signal is digitised and output as I&Q data streams.
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