We review the main underlying concepts of micropipelines before deploying them in real FPGAs.
How does a micropipeline work?
To visualize the behavior of an event-driven elastic pipeline versus a standard clocked pipeline, we will use the metaphor of the bucket brigade -- a method for transporting items by passing them from one stationary person to the next. The bucket brigade resembles the structure of a static data pipeline, in which data is passed from one register to the next.
A conventional synchronous pipeline is like a bucket brigade in which each member follows the beat of a clock. When the clock ticks, each person pushes a bucket forward. When the clock tocks, each person catches the bucket pushed by the preceding person.
Behavior of a synchronous bucket brigade.
By comparison, an asynchronous micropipeline behaves just as a real-world bucket brigade does. Each person who holds a bucket can pass it down the line as soon as the next person's hands are free. If there is no bucket available, the person waits for one.
Behavior of an asynchronous bucket brigade.
The particular behavior of micropipelines poses some great potential advantages over conventional synchronous pipelines.
- Speed: In a synchronous pipeline, the clock period must be slow enough to fit the slowest pipeline stage. In a micropipeline, each stage takes as much or as little time as locally needed. The micropipeline's speed depends on the average timing, rather than the worst-case one.
- Power consumption: In a micropipeline, the idle stages consume negligible dynamic power. In a synchronous pipeline, the clock is always running and drawing energy. A micropipeline power consumption figure depends strongly on the system data activity pattern, with the dynamic power being proportional to data throughput.
- Interference: In a synchronous pipeline, the clock's fixed rhythm broadcasts a strong interference signal at the operating frequency and its associated harmonics. In a micropipeline, there is no well-defined frequency, and any emitted energy is spread across the radio spectrum.
Now we are finally ready to build real asynchronous designs in commercial, off-the-shelf FPGAs. Just wait for the next blog in this series, because that's where we will start to get our hands dirty. In the meantime, do you have any questions?