As we march down the shrink roadmap, foundries are faced with the unenviable task of having to maintain their time-to-mask targets while managing the lithography related computational complexities and doing so with limited resources.
As we march down the shrink roadmap, foundries are faced with the unenviable task of having to maintain their time-to-mask targets while managing the lithography related computational complexities and doing so with limited resources. These challenges in turn establish three clear objectives for computational lithography suppliers:
- Providing innovative optical proximity correction (OPC) and resolution enhancement technology (RET) software and methodologies that achieve the maximum possible lithography entitlement
- Creating software, applications, and methodologies that allow foundries to increase their productivity and thus reduce development cycle times and associated costs
- Ensuring that the technology enables competitive turnaround time for the entire post-tapeout flow so that the foundries can manage their production costs and maintain the shortest possible mask data preparation time
These objectives have guided Mentor Graphics in developing advanced computational lithography technology. This year at the upcoming SPIE Lithography Conference, we will be talking about some of these new technologies and methodologies that we are developing with our foundry and IDM partners.
In this blog, I will specifically talk about four such initiatives.
First, improving productivity.
We've noticed that as we go down the technology nodes, the critical dimension (CD) measurement requirements to create accurate lithography models are exploding (see Figure 1).
(Source: Mentor Graphics)
Figure 1. The number of critifal dimension (CD) measurements are increasing with each process node.
This is due to several factors: 1) an increasing number of unique structures; 2) an increasing number of repeats across lot, wafer, and field; 3) an increasing number of process conditions.
Capturing the CD information by doing one-dimensional CD-SEM (scanning electron microscope) measurements then becomes a Herculean task.
A promising alternative is to use a SEM image based contour approach. This approach enables greatly increased model parameter space coverage and the ability to utilize more complex 2D information. The result is reduced metrology time leading to faster model development cycles.
In a publication with GlobalFoundries, "Bringing SEM-contour based OPC to production," by Weisbuch et al., the authors discuss the challenges of this approach and our solution.
Next, providing software and methodologies to enable resolution.
We have implemented a novel way of improving Optical proximity correction (OPC) accuracy when the mask error enhancement factor (MEEF) is large, which up to this point was considered a computationally infeasible task at the full chip level.
In the following paper at SPIE, "Model-based OPC using the MEEF matrix II," by Hong et al., the authors discuss this issue and our solution to the problem.
In a second paper for this category, "Resist toploss modeling for OPC applications," by Zuniga et al., the authors discuss the challenge of resist loss increases and resist patterns become more vulnerable to etching failures as CD sizes decrease for 32 nm technologies and beyond.
OPC models only consider 2D contours and neglect CD height variations. In this paper, we show that a Calibre CM1 resist model can be used to determine resist loss by properly selecting the optical image plane to calibrate to.
In addition, the paper will show how the model can be made more accurate by accounting for some 3D effects like diffusion through height.
Lastly, managing the post-tapeout flow.
Because Mentor sells integrated software for the full design-to-mask flow, we are always finding new ways of reducing the production cycle time.
While new cell-based, DP-aware, and timing-aware fill technologies provide designers with automated support for advanced fill requirements, late-stage design changes can extend tapeout schedules, due to the complexity of replacing fill, with its effects on file size, run time, and timing closure.
In this paper at SPIE, "Automated fill modification to support late-stage design changes," by Wilson et al., the authors present an ECO fill methodology, supported by fill tools, that quickly locates the affected area, then removes and replaces only the fill in that area while maintaining fill hierarchy. This new fill approach effectively reduces run time, contains file size, and minimizes timing impact, all of which are critical factors to ensuring time-to-market schedules are maintained.
So if you are involved in design for manufacturing or post-tapeout engineering, come out to SPIE this weekend to see these papers and many more, from February 23 through February 27, 2013 at the San Jose Convention Center.
— Gandharv Bhatara is the marketing manager for OPC group at Mentor Graphics.