It was late in the evening. I had just got the board assembled for a customer. When I went to program the device, I got hit with a warning that there was a high current draw and that the board most likely had a short. My first thought was that this might be due to the fact I was using 0.5mm pitch surface mount ICs and 0402 passives. Thus, I decided that it was in order for me to go through and retouch each solder joint to make sure there were no solder bridges. After doing this however, I got the same warning when I once again tried to program the device. At that time, I realized that I was in for a long night.
My first effort to fix what I thought was a soldering error had ended in frustration. It was time to get out more than the "calibrated eye." I resorted to my multimeter and confirmed that there was indeed a short across some of the nets. After an hour of experimenting and re-soldering components, I was no further ahead. At this point, I decided to take the components off of the board one at a time and see if I could get a visual on the problem. To my surprise, the short still existed. "Ah hah," I thought, the board manufacturer had made a mistake.
Two of the three offending boards. The top board was the first trouble maker.
(Click here to see a larger image.)
I then went on to test a few of the other boards that were in the lot to find that, indeed, out of a batch of 15 boards, there were three that had shorted traces. Having designed to their "allowables" (or so I thought), I did what any person might have done and shot them an email. To get these boards, I went through OSHPark. If you have not used them, then I highly recommend their services. The have good boards and offer good capabilities for very low volume prototyping boards.
My initial contact effort to OSHPark was not accusatory, but it was along the line of there is something wrong with the process that is not yielding parts that are consistent with the promised capabilities. Dan Sheadel got back to me promptly stating that there was an area in my board that had clearances that were under the allowable limits.
This is where my confusion started to set in. I had set my design rules checker to the OSHPark allowables, and I always ensure that I perform a design rules check just before I generate my Gerber files for manufacturing. How could I have had this error? I even went through the process of rechecking my design. I first checked my allowables, and I then checked to see if there were any errors. I even took screen shots to send back as a response to Dan showing that everything had checked out.
It was after I had sent my email, while I was looking through the screen shots, that I saw it. The setting to check for clearances around copper pours was turned off. I cannot say for sure that I did not turn that off, but I am 99.9% sure that I did not. No matter if this was the default setting or not, it caused me to design boards that were not compatible with the manufacturing process, and I ended up spending a lot of time trying to debug the problem.
Observe all the options that are unchecked by default!
(Click here to see a larger image.)
There are a few things that I would say are important to learn from this lesson. The first is the people that make your parts are part of your team. Their attention to detail and service is vital in trouble shooting issues. In this case, OSHPark had identified the issue in less than 12 hours from me sending in my first email looking for answers. Second, it is vital to understand your CAE tools. I think that CAE tool vendors do have a responsibility to not only provide software that works, but that is as intuitive as possible. Since many CAE vendors do not spend significant efforts to improve user interaction, the responsibility then falls to the user to attempt to understand their tools as best as possible.
Hopefully you will learn from my mistake and check all of the settings before performing your final design rules check. I know that I have learned from this experience. Have you run into anything like this yourself?