For watchers of emerging nonvolatile memory technology, the key paper in Session 19 at ISSCC 2014 in San Francisco, Calif., was the eagerly awaited 16Gbit ReRAM paper 19.7 "A 16Gb ReRAM with 200MB/s Write and 1GB/s Read in 27nm Technology" (Richard Fackenthal, Makoto Kitagawa, et al) that would report the results from a joint Micron-Sony team development.1
The 16Gb ReRAM used CuTe as the active memory material where in a CbRAM cell the growth and removal of a copper filament link through an adjacent thin insulator to a lower electrode provides the two nonvolatile (NV) logic states of the memory. As illustrated in Figure 1, the new ReRAM moved away from the conventional CbRAM structure and introduced a novel dual-cell memory structure. A structure where the top electrode, described as a common-source plate (CSP) is shared by a number of sub elements of the array architecture.
The two bottom electrodes, which require bi-direction writer/erase current, are driven by buried word line MOS select transistors. The memory cell size is 6F2.
Figure 1. The Dual cell ReRAM structure.
The headline characteristic for this new 16Gb ReRAM is the claim by its development team that with this device they have resolved the problems with earlier ReRAMs of either high performance with low bit density or low performance with high bit density and combined both high performance and bit density in one chip.
Based on a 27nm lithographic process using a 3-layer Cu interconnect system, the new memory die size is 168mm2.
Key performance characteristics are a read performance of 1GB/s and write of 200 MB/s. While details of the supply voltages Vcc at 1.2V and Vpp of 5V with an on-chip charge pump providing the 6.6v required for programming. However, conspicuous by its absence were the details of power dissipation at the reported write/erase performance levels or for that matter the value of the bi-directional write/erase current needed and provided by the buried MOS selector transistors.
The architectural subdivision for the 16Gbit ReRAM is illustrated in Figure 2.
Figure 2. The basic architecture of the 16Gb Micron-Sony ReRAM.
Each bank is divided into eight strips that are vertical groups of tiles with a common global bit line. A Y strip is divided into 16 tiles plus a redundant tile, with each tile consisting of a matrix of 8,192+256 local bit lines and 2,048 word lines resulting in a tile size of over 16Mb. During the sense program operation eight tiles (one per Y strip) are activated simultaneously, each accessing a sub page for what is described as a total sense currency of 512 +16 cells.
The chip has two interfaces one described as a high-speed LPDDR-like 1GB/s user interface and the other a low-pin-count test interface to facilitate high levels of parallel wafer testing.
Programming or write occurs in eight tiles simultaneously, each with one active sub-tile, where each sub-tile can program or sense up to 66 cells. Within the design provision is provided for iterative or multiple pulse set operation. The authors acknowledge that raising the voltage of the CSP for set operation requires significant energy and to minimize this as a problem the charging of the CSP is inhibited on sub-tiles where only a single set pulse has been sufficient to set the device. The inhibit will occur when a set verify signal is received and it is claimed this is likely to occur on the second or third attempt at set because most devices will set on the first pulse.
There are three options for the sense amplifier and they are read sense, set verify or reset verify, the latter two used during programming.
The sense amplifier is a differential current mirror design that employs three transistor types. An MNOS transistor is used to set the the three different sense reference current levels required for read, set verify, or reset verify. The design uses both thick and thin oxide MOS transistors. The thick oxide devices serve two purposes, the primary one is to protect the thin oxide cascode devices from the 5V required for programming, the other role is to reduce the drain capacitance presented to the current mirror devices. The thin oxide transistors are the part of the cascode-based design that sets the bit line voltage and are employed to minimize mismatch, reduce bit line offset, and speed up bit line charging. The output from the sense amplifier uses a comparator to restore the logic levels.
The new 16Gbit ReRAM shown in Figure 3 is an impressive piece of design and a clear demonstration of lithographic and fabrication skills. With an array design that that might be serves as a vehicle that will allow other CbRAM types of ReRAM to be evaluated, for example Ag-a-Si.
The absence of important details for this implementation of power dissipation, read write/erase current values, write/erase lifetime, and elevated temperature data retention would suggest that the appearance of this device in standard product form is still some way ahead.
Figure 3. The finished chip approx 18 x 9 mm (168mm2). (Source: ISSCC paper 19.7)
— Ron Neale blogs about memory and reviews ISSCC papers for EE Times's Memory Designline.
1. ISSCC 2014 Paper 19.7 "A 16Gb ReRAM with 200MB/s Write and 1GB/s Read in 27nm Technology" by Richard Fackenthal,1 Makoto Kitagawa,2 Wataru Otsuka,2 Kirk Prall,3 Duane Mills,1 Keiichi Tsutsui,4 Jahanshir Javanifard,1 Kerry Tedrow,1 Tomohito Tsushima,2 Yoshiyuki Shibahara,4 Glen Hush.3 1Micron, Folsom, CA, 2Sony, Boise, ID., 3Micron, Boise, ID, 4Sony, Kanagawa, Japan, Proc ISSCC 2014.