The AsyncArt Project was born in the year 2006 as an entrepreneurial project targeted to take commercial advantage of the benefits that come with applying asynchronous logic techniques to commercial-off-the-shelf FPGAs. After being closed due to lack of funds, the AsyncArt project was offline until 2012, at which time it resurfaced in the form of an open hardware initiative.
Editor's Note: This article first appeared on Programmable Planet, which was a thriving community website devoted to all things programmable. Sadly, PP is no longer with us, but many friendships were forged there that will last for years to come.
The main AsyncArt deliverables are a set of demo examples that illustrate the general building blocks of an efficient asynchronous design flow targeted at FPGA devices. The basic circuitry running under the hood of these examples is strongly inspired by Ivan Sutherland's micropipeline concept, which I introduced in my previous blog.
FPGA technology is crucial to the AsyncArt project as an affordable and flexible tool for both research and educational use and commercial production. Thus, the main focus of the AsyncArt project is on deploying asynchronous circuits over programmable logic devices.
It's worth noting that, once tested in an FPGA, a design based on the AsyncArt libraries can be successfully migrated to custom CMOS technology. In order to demonstrate this, in 2007, a prototype chip called the PNX1 was built by the Public University of Navarre through the MOSIS program in collaboration with the New Mexico State University.
A panoramic view of the PNX1 test chip
(Click here to see a larger image.)
If you want to learn more about this project or if you are interested in giving asynchronous logic in FPGAs a try for yourself, you can download up-to-date reference designs and libraries from the official AsyncArt website, which is hosted by CERN's Open Hardware Repository.
In order to provide a good out-of-the-box experience, the released reference designs have been standardized by porting them to a free-to-use project development environment. The AsyncArt project deliverables are thus full Xilinx ISE 14 projects, all of them consisting of a collection of demos comprising two fundamental elements:
- TOP-Level Schematic: Schematic design entry has been selected for the top-level design as being conscious of the geometry and dynamics of the whole system -- a key issue in order to cope with the specific asynchronous logic issues. DESIGN TIP: the “keep hierarchy” property is a useful tool in order to get a “what-you-see-is-what-you-get” behavior, as some synthesis tools may break the asynchronous control logic.
- HDL TestBench: In order to make the first approach easier, every included schematic is accompanied by a testbench that is ready to be simulated. This testbench contains information related to the expected outcomes that should be observed from the simulator. DESIGN TIP: Real physical behavior is required for getting an asynchronous circuit running as expected. In this way, post Place and Route models need to be used when in simulation.
To further whet your appetite for asynchronous logic, the following screenshots are taken from the AsyncArt's "micropipelines" demonstration project.
In the demonstration above, an eight-stage micropipeline FIFO has been implemented. When the circuit is active, an 8-bit counter starts to serve data tokens to the pipeline, which moves them as fast as possible towards a destination sink. This design may be used as a reference for building elastic (variable data load) buffers in packet processing systems.
In the above demonstration, a more complex micropipeline is constructed, including different branches and internal data processing. Here, two different 16-bit counters insert data tokens into their associated input micropipeline segments. Next, the two incoming data streams are summed, and the result is triplicated and driven towards three different output micropipeline segments. This design is a first step toward demonstrating how micropipelines can be used to build DSP architectures.
In the demonstration above, we have a micropipeline in which conditional data steering is implemented. A 16-bit counter inserts data tokens on the input micropipeline segment. Then, depending on the data value, the micropipeline control chooses one of four different output pipeline segments for the data. This design may be used as an example for implementing an asynchronous network-on-chip (NoC).
In the above demonstration, we have two different input micropipeline branches that produce data tokens when their respective control signals change. In the middle of the design we can see an asynchronous arbiter; this joins the data streams from the two input micropipeline segments and sends all of them to the output segment in rigorous incoming order. This design may be used as an example for building interrupt collectors or more complex asynchronous network-on-chip (NoC) topologies.
Well, I'm sad to say that our brief excursion into the clockless domain has ended... for the moment. Please post any questions below, and don't hesitate to contact me if you want to know more about the thrilling technology that is asynchronous logic!