Many of today's semiconductors do a great job in circuit designs for measurement applications. ADC (analog-to-digital converter) and DAC (digital-to-analog converter) devices offer astounding resolution and throughput speed. Wide-bandwidth amplifiers now offer low drift and excellent stability. When you combine these analog components with the latest FPGA or MCU devices, you bring incomparable measurement capability to today's systems.
Unfortunately, it's easy to overlook another important "component," the PC board, which combines these devices into a relatively noise-free signal processing function, but only if properly designed.
When placing devices on a board, you must take great care and use a well-thought-out strategy for dealing with noise generation, clock spill-over, heat diffusion, analog lead lengths, connector egress issues, and software assists to minimize data sampling at critical time intervals. The PC board has become one of the most important parts of an analog design.
What does it take to get maximum performance and low-noise operation from an analog system? Assuming the circuit design is largely finished from a theoretical standpoint and is about to go to CAD for layout, the first step is a placement of the devices. The figure below shows the parts placement for a DT9829 board.
Careful placement of analog and digital components can maximize performance by minimizing noise and thermal issues.
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First, you must make sure that the circuitry fits in the size required. Then, the strategy becomes more involved, becoming a "what if" game. That is, which devices interfere with other devices, which leads pick up noise by being too close to other leads, and which devices throw off heat to cause thermal errors? Separation of analog and digital return paths becomes paramount to avoid ground loops. Furthermore, you must deal with switching-power-supply circuits to minimize EMI/energy transfer into critical analog lines.
Now, I haven’t mentioned ESD and EMI emissions and immunity problems that can show up in later testing. If these are not considered upfront, no amount of testing will overcome these liabilities. In addition, stressing of the board can cause aberrant data. This also must be considered.
These steps of figuring out possible sources of error pay huge dividends. You can eliminate extra board spins and lengthy time sinks at this point. Of course, experience is the best teacher.
We have seen many of these error sources from many designs. Taking the time to understand these critical error sources can save money and time down the road. Also the joint overview of the CAD design between the responsible design engineer and the CAD designer is needed to get the best solution.
This is our approach to dealing with the most important component in our designs. What's your approach?