When migrating to a new node, circuit reliability is a concern: Physics involved may change as process dimensions change, but is your design robust against electrical circuit failure?
We've written before about circuit reliability, and the challenges of putting in place a verification strategy to identify sources of possible electrical circuit failure before they happen.
Recent product recalls highlight the fact that this type of failure can be quite sinister and difficult to detect. In fact, an integrated circuit (IC) may not fail immediately on a test bench, but several weeks or months after those circuits are deployed, which is an exponentially more expensive problem to fix.
A common question that I am asked is, "What challenges will migrating to a new node pose?" For to circuit reliability, the answer is two-fold. First, newer nodes mean smaller feature sizes, as well as thinner oxides and wires, which means greater susceptibility to electromigration (EM) and electrical overstress (EOS), due to the sensitive nature of the devices and the wires. However, more importantly, circuit reliability is a concern at all nodes, and is not something that only leading-edge designers have to face.
Electrostatic discharge (ESD), latch-up, EOS, EM, differential pair matching, etc., are all issues that designers must face across a range of process nodes. While the physics involved change as process dimensions change, the overall concern is the same "Is my design robust against electrical circuit failure?"
One area that we see a lot of interest in across all nodes is voltage-aware (or voltage-dependent) DRC. The reason for this interest is that higher voltages between two polygons or wires require larger separation distances to ensure the reliability of the silicon. If you only have one set of DRC rules, then you must implement the most conservative spacing checks based on the highest voltage differential that your integrated circuit will experience. For most customers designing across a range of voltage regions, this approach is too pessimistic, and leads to a lot of wasted circuit area.
A common method of mitigating these issues is to implement different checks for different voltage regions. To enable these checks, however, the user must intervene and manually generate "marker layers" or text points that inform the DRC tool as to what voltage region the wires or polygons reside in, and therefore, which spacing checks to perform.
There are two shortcomings to this method. First, user intervention is always problematic, because it introduces another possible source for error, either in identification or in voltage assignment. Second, this technique, especially the use of marker layers, takes a fairly broad approach. Even if the marker layer is assigned appropriately to a high voltage region, it cannot determine whether two adjacent wires will actually experience the maximum voltage differential. I have heard the following complaint on a number of occasions, "These two nets will never swing rail to rail [VDD to VSS], but I have to keep them at max separation to be DRC-clean."
We have worked with our customers and the foundries to establish voltages for nets throughout the design, and to use that information to drive more efficient DRC methodologies. I am curious if any of you are incorporating techniques for voltage-aware or voltage-dependent DRC. If so, what techniques are you using, and are there any best-practices that you would advocate?
— Carey Robertson is a Director of Product Marketing at Mentor Graphics Corp., overseeing the marketing activities for Calibre PERC, LVS, and extraction products.