The four main challenges of DRAM are to satisfy bandwidth requirements, reduce power consumption, maintain low cost, and now, with the rise of mobile devices, have a small footprint. DRAM has been meeting industry demands by steadily shrinking the cell size, reducing its operating voltage while maintaining the minimum capacitance of 25 fF for reliable sensing of signals. Shrinking the cell size enables higher memory density and thus reduces cost, but below the 30 nm node, shrinking the cell may not be economical because of the need for multiple patterning, and the use of new materials increase the R&D and manufacturing cost.
If scaling has hit a memory wall due to economic reasons, then what is next? In this article, some of the challenges faced by memory makers as they strive for sub-20 nm devices are discussed.
In the last IEDM 2013 conference, the invited paper "Challenges in 3D Memory Manufacturing and Process Integration" by N. Chandrasekaran from Micron (subscription required) stated that other alternatives to DRAM and NAND are not yet manufacturing ready and are far from providing competition in the application space of DRAM and NAND. This means that the future of DRAM and NAND devices below 2x nm nodes is not on an easy path, but rather one fraught with challenges. The solution to the memory wall has to be found from the current memory devices.
Increasing memory density with minimal scaling
In particular for DRAM, the scaling has become so difficult that the industry leaders are constantly adopting new process technologies. The parameter that defines a new technology node is also changing. Samsung, at the 3x nm node, decided to take the half the shallow-trench-isolation (STI) pitch as the defining parameter for the technology node. From its point of view, it is the smallest pattern-able feature, and thereafter SK-Hynix followed suit. However, Micron still uses the conventional definition for the technology node, which is the half wordline pitch. But no matter how the technology node is defined, the cell size and the memory density can always be used for benchmarking. If memory density (Mb/cm2) is considered, then the Samsung 2x nm LPDDR3 packaged device made a gigantic leap from its previous generation by moving from the planar 2D to the 3D option.
3D memory devices can be classified into two categories. The first one is applicable for 3D NAND devices, where the storage bits are stored vertically in thin silicon layers stacked one on top of the other. But this technology process cannot be applied to DRAM due to the high aspect ratio capacitors. So the second approach is to stack several dice in a package to increase the memory density without increasing the package area.
In 2013, TechInsights analyzed the Samsung 20 nm class 3 GB LPDDR3 DRAM device. This is a multiple chip package (MCP) containing six memory dice. The Samsung 2x nm 3 GB LPDDR3 packaged device is the first DRAM device in the 2x node and the first in the industry to have a memory density of 3 GB in a single package. The Samsung 3 GB LPDDR3 mobile DRAM MCP contains six 2x-nanometer (nm) class four-gigabit (Gb) LPDDR3 dice, as two stacks of three chips in a single package. The package is only 0.8 mm thick. This is even less than the package thickness of its previous-generation 30 nm class 2 Gb DDR3 DRAM containing one die.
Figure 1 shows an X-ray image of the Samsung 2x 3GB package. The two stacks of three wirebonded dice are clearly seen. The total memory capacity of the package is 3 GB (4 Gb x 6 = 24 Gb; 24 Gb ÷ 8 = 3 GB).
Samsung 2x 3GB LPDDR3 package, showing six dice of 4 Gb each arranged in two symmetrical stacks to give a total memory of 3 GB.