To put six dice in a package without increasing the total package thickness implies that the individual dice are thinned considerably; this has been done for FLASH devices but is not commonly seen for DRAM. Dice thinner than 50 µm create problems with wafer handling and warpage.
Figure 2 shows the die thickness of several generations of Samsung DRAM, which have been analyzed at TechInsights, showing the dramatic decrease in die thickness for the 2x nm die.
Die thickness of several generations of Samsung DRAM.
Samsung has achieved a doubling of memory density in its transition from 3x to 2x while keeping its 6F2 cell layout. Figure 3 presents the die efficiency and the memory density over several generations.
Die efficiency is the total memory cell area divided by the total die area in percentage. It can be seen from the graphs that the die efficiency is slowly increasing with each technology node. This means that the memory area is increasing and the periphery area is decreasing. But the Samsung 2x nm 4 Gb LPDDR3 die has a spectacular 45% increase in memory density as compared to the 3x node. This new 2x nm has a die area of 39.7 mm2, which is 9% larger than previous generation 3x nm 2 Gb DDR3 die area, but the memory capacity of the 2x nm die is double that of its previous 3x nm generation.
Evolution of die efficiency and memory density over several generations of Samsung DRAM.
Figure 4 summarizes the main differences between the 3x nm 2 Gb DDR3 die and the 2x nm 4 Gb LPDDR3. Both generations use the buried wordline (bWL) concept, with the 2x nm device being a shrink version of the 3x nm device. The active islands (AI) are slanted 20˚ from the bitline (BL) direction for both technology nodes.
The new 2x nm device's active islands are 25% shorter and 7 nm closer to each other than the previous generation. Similarly, the wordline (WL) pitch and the bitline (BL) pitch of the 2x nm device are 29% and 18% smaller than that of 3x nm device, respectively. The 2x nm device is a little more than half that of the 3x nm cell (0.005 µm2 and 0.0086, respectively). The pitch of the active islands is also the pitch of the STI, and half of this measurement is the smallest patterned feature. The 3x nm 2 Gb DDR3 die and the 2x nm 4 Gb LPDDR3 have STI pitches of 60 nm and 52 nm, respectively. These define the technology nodes as 30 nm and 26 nm, respectively.
Cell Layout of Samsung 3x nm 2 Gb DDR3 and 2x nm 4 Gb LPDDR3. Both generations use the buried wordline (bWL) concept. The 2x nm is device is a shrink of the 3x nm device.