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20nm Dilemma Explained

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AKH0
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Re: Bulk Si, FDSOI and FinFETs
AKH0   4/20/2014 10:03:17 AM
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TSMC's 16nm technology has a gate length of 30nm or more. Same is Intel's 22nm. The cross sections have been clearly shown in conferences. 10nm platform that you quote also has a gate length of more than 20 nm as will be shown in June. This is the first time I hear FinFET does not need strain and strain is bad. Please talk to people that run wafers. Whether it's most of the current in the top or all of it, at the end of the day what matters is current per capacitance or gm divided by capacitance. If you do that math FinFET comes shy. Please see broadcom's invited paper at iedm 2013. FinFET ft - even intrinsic , which is simply 1/2pi gm/Cgs comes worse than 20nm planar. We can talk all day how beautiful a PowerPoint FinFET is. But the fact is that one by one people are seeing its problems.

michigan0
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Re: Bulk Si, FDSOI and FinFETs
michigan0   4/20/2014 12:40:45 AM
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Sang Kim

 

You disagree that 14nm technology means a 14nm gate or

channel length for 14nm FinFFETs. You said that is not true,

known across all companies. "The technology node number

is just a label.......... ." I can't disagree more. When Intel

and TSMC announced 14nm and 16nm FinFETs respectively

for high volume manufacturing in 2015, they meant 14nm

and 16nm channel or gate length, Lg. 2014 VLSI symposium

featuring a 10nm FinFET platform means a 10nm channel or

gate length, Lg. Otherwise, we can't talk about transistor

leakage current or short channel effects that are the

determining factors for FinFET scailerbility.

 

You miss quoted me here. I didn't say "only the top of the

channel....." I said most of the high I-on current comes from

the upper narrow portion of FinW(width) because the narrow 

region is fully inverted....etc." An important thing to 

remember here is that not the entire FinW area is inverted. 

Because of a trapezoidal nature of Fin shape, FinW at the

bottom is much wider. Therefore, the FinW at bottom is not 

inverted, instead depleted. That is why the high I-on current 

comes from the upper narrow inverted FinW region. FinFET 

doesn't require an additional strain knob that may impact 

adversely the un-doped inverted Fin region. That is why

Intel's 22nm and 14nm FinFETs in volume manufactured 

today don't use additional strain. The maximum high I-on 

current for Intel 14nm FinFET is achieved by maximizing 

the un-doped upper fully inverted FinW region and 

minimizing the fully depleted FinW region at bottom. 

 

   





AKH0
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Re: Bulk Si, FDSOI and FinFETs
AKH0   4/19/2014 4:20:29 PM
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Dear Sang Kim. You are making the assumption that 14nm technology needs a 14nm gate length, which is not true. This is know across all companies. The technology node number is just a label, without any direct connection to any dimension on the device. I agree embedded SiGe is not doable on FDSOI, and that's why I used SiGe in the channel, with performance competing with anything that is out there. However, I do not agree FinFET does not need a strain knob. It does and as far as I have seen (experimentally and by analyzing data from Intel and TSMC so far) eSiGe does NOT work the way it used to. The explanation you provided as only the top of the channel conducting the current actually makes things worse. You are paying the capacitance penalty for the entire gated portion of the fin, so if only the top portion really conducts it's less current for a given capacitance.

michigan0
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CEO
Re: Bulk Si, FDSOI and FinFETs
michigan0   4/19/2014 4:04:10 PM
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Sang Kim

 

The 3.5nm SOI thickness for14nm FDSOI is estimated from 

simulation data published by Professor J. G. Fossum, 

university of Florida in his book "Fundamentals of Ultra-thin

body MOSFETs and FinFETs". See Fig. 3.8 on FD/SOI 

MOSFET with thick BOX.

 

In my opinion even with 6nm SOI thickness for 14nm 

FDSOI the 6nm SOI is too thin to incorporate SIGe for PFET 

in order to be effective. FinFET dose not require a strain 

knob for PFET as well as NFET. Fin-Width has a trepizoidal 

shape that means the Fin-Width decreases with Fin-Hight. 

As a result, most of the high I-on current comes from the 

upper narrow portion of the Fin because the narrow region 

is fully inverted just like double gate transistor. For double 

gate transistor the hightest transistor on-current occurs 

when both top and bottom transistors become inverted.

 

According to just published 2014 VLSI abstracts the 14nm 

FDSOI with forward back bias(FBB) is not manufacturable 

yet, just demonstration. I doubt it is manufactured.

 

I repeat FDSOI has not been volume manufactured at any 

technology yet, and will not be. Major semiconductor 

companies will adopt FinFETs, not FDSOI.  




AKH0
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Manager
Re: Bulk Si, FDSOI and FinFETs
AKH0   4/10/2014 10:53:07 AM
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I am not sure where you get the 3.5nm thickness from. Although it is a great improvement over 6nm vs 12nm argument you were making not long ago. As publicly stated multiple times and will be shown at VLSI symp in a few months, 14nm FDSOI is using 6nm channel thickness. It uses Si channel for NFET and SiGe for PFET. NONE of the FinFET devices published so far have a strain knob for PFET despite all the performance claim and continue to normalize the current per footprint which I consider cheating as a device engineer - this is exactly how TSMC claimed performance parity or even advantage over Intel 22nm. And by the way there is no 16nm or 14nm gate length in 16nm FinFET technology. The shortest gate length in FinFET is 30nm and low leakage devices go all the way to 50nm. Please see TSMC's paper. Those rule of thumb thickness versus gate length don't come into play when you design technology relevant devices. And believe me I did this for both FinFET and FDSOI for more than 6 years.

michigan0
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CEO
Bulk Si, FDSOI and FinFETs
michigan0   4/9/2014 9:19:35 PM
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Sang kim

 

Here are some of the important facts on differences of Bulk Si,  

FDSOI and FinFETs. 

 

Bulk Si successfully ran several technology nodes such as 95, 

65, 45, 35 but ends at 28nm. In order to suppress transistor 

leakage current or drain/source punchthrough a combination 

of channel doping and retrograde channel implant just below 

the Si surface were used for Bulk Si. However, such a 

combination of the channel doping and retrograde implant 

has a limit as the channel or gate length, Lg decreases to 

20nm because precise control of shallower retrograde channel

implant just below the Si surface becomes increasingly more

difficult, complex and not so effective any more in 

manufacturing, resulting in high device variabilities or 

instabilities in transistor electrical transfer characteristics due 

to high transistor leakage current due to poor process control 

and manufacturability. That is why Intel adopted 22nm 

FinFETs.    

 

FDSOI is not the cost issue but transistor device physics 

issue.  FDSOI has two most critical issues: its scalerbility and 

manufacturability. IBM invented FDSOI technology over a 

decade ago and created International SOI consortium to 

develop and manufacture FDSOI but not manufacturable 

today at any technology node yet. IBM exited FDSOI a long 

ago.  

 

FDSOI has such a very simple structure consisted of high K

metal gate, thin SOI and thick oxide substrate that often 

make unware of the real issues with FDSOI. The 28nm 

Bulk is in mass production for several years by major 

semiconductor companies such as Intel, TSMC, Samsung 

and others but 28nm FDSOI is not manufacturable today. 

Even if manufactured today, it would not be 

competitive with 28nm Bulk because SOI wafe rcost is 

very much higher than bulk Si wafer. 

 

FDSOI is not scaleable. The beauty of FinFETS over FDSOI 

is its scaleability. The thin SOI is the key component of 

FDSOI to suppress transistor leakage current or short 

channel effects. In order to suppress transistor leakage 

current for 20nm FDSOI a 5nm thin SOI is required while 

for 20nm FinFETs the Finwidth at the bottom of Fin that is 

equivalent to SOI thickness for FDSOI requires 20nm. 

What a large difference! 20nm for FinFETs vs 5nm for 

FDSOI for suppressing transistor leakage current or short 

channel effects. That is why Intel's FinFETs are scaleable 

to the end of the roadmap, but not FDSOI, not even 14nm 

FDSOI that requires 3.5nm SOI that is close to the 

ultimate quantum confinement limit(3nm). That is why 

Intel 14nm FinFETs will be high volume manufactured in 

2015 at the same time when TSMC 16nm FinFETs volume 

manufacturing starts. Major Semiconductor companies 

will adopt the FinFETs, not FDSOI.



rick merritt
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Re: SOI users at 20nm?
rick merritt   4/9/2014 10:35:05 AM
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@SOI Lady: I am assuming you mean GloFo which said in the past it would support the process.

No doubt there is some busienss being a second source for ST...but as Austin Tech Watcher noted, there seems to be a diminishing set of supporters.

rick merritt
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Author
Re: SOI users at 20nm?
rick merritt   4/9/2014 10:32:39 AM
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@Austin Tech Watcher: Thanks for the good perspective, David!

Austin Tech Watcher
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Re: SOI users at 20nm?
Austin Tech Watcher   4/8/2014 4:29:51 PM
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IBM uses SOI for its Power processors. Your point is valid: Freescale stopped using SOI because of gaps in the design IP, and AMD also retreated. It is hard to gain back the cost of the wafer for $20 chips, I was told.

JeffL_2
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CEO
Re: STM micro bias
JeffL_2   4/8/2014 12:15:24 PM
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"All the industry is going to FinFet, following Intel that has a three years lead and experience"...

Oh sure, I mean Intel has a PERFECT record on process selection, they've NEVER jumped on a technology before it was "ready for prime time" and regretted the consequences, have they? Oh and by the way has anybody seen my bubble memory USB key, I think I must have misplaced it somewhere...hmm!?

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