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20nm Dilemma Explained

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Gondalf
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Re: FD-SOI and AMD
Gondalf   4/5/2014 6:11:25 PM
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No Amd has shifted to bulk definitively.

The STM micro bias has omitted the necessity of dual patterning at 20nm FD SOI, double patterning and some quadruple at 14nm FD SOI etc....

The interconnection thikness is not related with the type of transistor and with exotic substrates. 

The real cost is in interconnection and most of the costs of research are devoted to its improvement at the finest nodes.  

Fottemberg
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FD-SOI and AMD
Fottemberg   4/5/2014 5:13:56 PM
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Will AMD produce CPUs or GPUs on FD-SOI during 2014?

Gondalf
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STM micro bias
Gondalf   4/5/2014 3:59:50 PM
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Estimated....estimated....estimated.

Nobody knows the real wafer cost at TSMC or Intel on 22/20nm , not even STM.

Moreover STM has yet to give hard numbers about superiority of FD SOI versus FinFet in high power, medium power, low power, very low power transistors.

STM is obscure....smoky. What about the comparison between FD SOI and Bulk??? why not between FD SOI and Bulk + FinFet ??? strange thing indeed !!

All the industry is going to FinFet, following Intel that has a three years lead and experience over all contenders in high volume shipment of FinFet devices.

I assume that Intel has chosen FinFet over SOI because it gives the better performance, the lower power consumption and the lower per wafer cost at 22/14/10nm nodes.

No matter what is saying STM, all the foundries have done definitively their choice.......FinFet. The history is written right now.

resistion
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Self-heating
resistion   4/4/2014 9:46:42 PM
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Although double patterning is certainly a signficant barrier, a more aggressive shrinking (<0.7x) could bring back some more returns. Actually, the greater concern for me is the self-heating that could be aggravated in these thin silicon devices (FDSOI and FinFET). It's harder for heat to move away from hot spots in thin silicon. Even in the Intel trigate case, it has to move down from the narrowest point (the apex).

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