From the 28nm technology node going forward, the FPGA industry needs to open up for a broad range of innovation so as to continue offering better products.
In my recent blog, 28nm: The Last Node of Moore's Law, I outlined the recent dramatic change that has occurred after many years of cost reduction associated with dimensional scaling. It is now clear that the 28nm technology note will provide the lowest cost-per-gate for years to come. In this blog we will assess the potential implications for the ASIC and the FPGA markets.
Over the last two decades, we have seen escalating mask set costs associated with dimensional scaling, along with accordingly escalating NRE costs. At the recent 2014 SEMI Industry Strategy Symposium (ISS), Ivo Bolsens, Xilinx CTO, presented the following chart illustrating ASIC design cost escalation:
The dramatic increase in ASIC design costs have had a real effect on the ASIC market, reducing the number of new designs and dramatically reducing the number of vendors serving the ASIC market. One would expect that such a trend would have a very positive effect on the FPGA market. This is because there is no mask-set cost associated with an FPGA design and, accordingly, far lower NRE costs per design. The following fictitious chart (which was presented in the EE Times article: What's the number of ASIC versus FPGA design starts?) illustrates these expectations:
Surprisingly, this did not really happen. The following chart presents the overall FPGA market during the last decade according to the financial results of Xilinx, Altera, and Actel:
The FPGA market growth could be compared to the overall semiconductor market growth as presented in the chart below (the market in 2013 was $305B). Clearly, the FPGA market growth during the last decade is similar to the overall semiconductor market growth, and there is no indication of any benefits devolving onto the FPGA market from the escalating ASIC mask-set costs and associated NRE.
FPGA technology began in the mid-1980s as an alternative to the popular ASIC technology of that time -- the Gate Array (GA). The acronym FPGA stands for Field-Programmable Gate Array. During the 1990s, the Gate Array ASIC technology lost its appeal as more sophisticated ASIC technologies came to the fore, and the ~$20B Gate Array market shrunk dramatically until it effectively ceased to exist. Analysts expected that this would have a dramatic positive impact on the FPGA market, which did grow to some extent, but far less than everyone's expectations. The trend of escalating NRE driven by dimensional scaling and escalating lithography costs kept on going into the 2000s and drove down the number of ASIC designs. Once again, analysts expected a huge surge in the FPGA market, but -- clearly -- this did not happen.
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