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FPGAs as ASIC Alternatives: Past & Future

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TanjB
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Mask costs seem quite small
TanjB   4/21/2014 5:15:07 PM
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You suggest mask costs as a driver for a switch to FPGA, but your chart does not show mask costs to be dominant.  The "design" part of the chart shows the most dramatic growth as designs scale down.  Why is that, what are the contributions to the rise in design cost?  How do the costs break down in FPGA vs. other semis?  Have design costs scaled less for FPGA?

I would think that time-to-market would be a bigger driver than mask costs.  After all, for FPGAs to become a large part of the market they would need to be made in large volumes, at which point their larger size and cost per function would easily overhang the mask costs.

Time to market can be very expensive in terms of opportunity cost.  Plus, the big SOCs these days have everything and a kitchen sink thrown onto the die - just power down the parts you do not need.  This competes indirectly with FPGA, where you also buy oversized silicon in order to get just what you need.  Finally, in a low power world where mobile devices of all kinds are the growth drivers, are FPGA coming in at low enough power, even if they ace the rest of the problem and you can reach market fast?

I would guess that the strongest parts of the market for FPGA are things which FPGA excel at, like reconfigurable signal processing, or system prototyping, or low to mid volume specialized pipelines.  The things they have always been good at, rather than displacing other segments of the market?

DF0
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FPGA vs. ASIC
DF0   4/21/2014 7:40:34 PM
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"In this paper, we have presented empirical measurements quantifying the gap between FPGAs and ASICs for core logic. We found that for circuits implemented purely using the LUT based logic elements, an FPGA is approximately 35 times larger and between 3.4 to 4.6 times slower on average than a standard-cell implementation." [emphasis mine]


Most contemporary FPGAs have a lot of specialized logic.  These parts contain components such as memory blocks, Multiply-Adders, high-speed PHYs/MACs, etc.  Altera and Xilinx even make parts that combine what's essentially an ARM SoC with a programmable fabric.  On designs that can benefit from these components, like signal processing chains, the FPGA penalty is considerably lower.

Or_Bach
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EE Time Recent Survey
Or_Bach   4/22/2014 3:22:02 AM
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Just published EE Time survey <http://www.eetimes.com/document.asp?doc_id=1322014> report an interesting trend: "FPGA use is trending steadily down from 45% six years ago (not shown) to 31% last year," - it seems supporting this blog conclusion 

Quix0
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Prototyping vs Production
Quix0   4/22/2014 7:01:02 AM
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As the title suggests the author is focusing on use of FPGAs for production quantities - which may be dominant segment for FPGA companies in terms of revenue. I can see how the trade-offs work out between FPGA and an older node make sense for production use. The suggested solution seems to target this.

Where FPGAs are used for ASIC prototyping the concern we face is performance slow-down which prevents us from running a real-time prototype. E.g. prototyping an ASIC targeted to 40nm std cell design when prototyped on an FPGA device using 28nm, I have seen slow down of 10X to 30X. Are there any efforts on to solve this issue?

fundamentals
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FPGAs as ASIC Alternatives
fundamentals   4/22/2014 11:55:39 AM
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I am one of those who is old enough to remember similar statements about 1.0 micron, 0.35 micron, and 0.18 micron CMOS technologies.  The past claims that these technologies were going to be the bread-and-butter of the industry and provide lower cost for years to come has proven false.  I predict that the same thing will happen to 28nm too.

The march to smaller technologies may slow down a bit, but it will continue.  Today 14nm chips may be more expensive than 28nm chips due to yield issues. But that will change in a few years (less than five!)  The mask costs will always be high, but the mask costs are irrelevant to FPGA vendors.  They only care about wafer costs and yield.  The mask costs hurt ASIC starts, but they have very little impact on FPGA development or FPGA pricing.

DougInRB
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Speaking of Gate Arrays...
DougInRB   4/22/2014 2:16:10 PM
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I'd like to see some predictions of how Toshiba's "Fit Fast Structured Array" will impact FPGA growth.  These seem to be pin compatible FPGA replacement gate arrays with very low NRE.  If this technology takes off, FPGA volumes could be impacted dramatically.

Also, what are the FPGA companies dreaming up in terms of true innovation that breathes life into programmable logic?

 

betajet
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Re: Speaking of Gate Arrays...
betajet   4/22/2014 3:03:34 PM
Doug asked: Also, what are the FPGA companies dreaming up in terms of true innovation that breathes life into programmable logic?

JMO/YMMV

From what I read here at Geek Times, it seems that Xilinx and Altera are mostly making their FPGAs even more expensive and trying to use marketing to convince customers that putting more functionality into programmable logic is a solution to their problem.  My ambiguous use of the word "their" is deliberate.

I'm seeing innovation from Lattice, especially the Silicon Blue devices.  (I've looked at the architecture but haven't designed with them yet.)  There is a need for small, really cheap FPGAs.  I've used Actel -- now Microsemi -- ProASIC3 and Igloo and they're good, but pretty expensive.  Lattice could very well grow its market share by coming up from the bottom -- I'd keep an eye on them.

IMO, what's suffocating FPGAs is the fact that no FPGA vendor (except for Atmel, long ago) publishes the internal details necessary for people to write alternate programming tools.  This makes it difficult for people to get started creating things with FPGAs, since the available tools and languages have very steep learning curves.  Now if you're working with FPGAs all the time you get used to the tools and after you've learned the various tricks FPGA design becomes easy and you don't appreciate what a new user faces.  But if FPGA vendors want to get new users, that learning curve has got to come down.  Since their marketing keeps saying how easy it is to design FPGAs, they don't seem to recognize that they have a problem.  So I see the only solution as opening up the bitstreams so others can breathe life into FPGAs.

I recently watched an on-line discussion as to which was worse, VHDL or Verilog.  This was like watching a debate as to whether Fortran or Cobol was worse for writing an operating system, with the assumption that the CPU manufacturer didn't document the machine language so you could only program your CPU using one of those two languages.  IMO, that's where we are with FPGA design.  Stifling, isn't it?

JMO/YMMV



DougInRB
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Re: Speaking of Gate Arrays...
DougInRB   4/22/2014 3:56:41 PM
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I thought we were going to see 'true innovation' from the likes of Achronix.  It appeared that they were going to provide us with a programmable device that had amazing performance by utilizing asynchronous design techniques.  However, when I look at their datasheets I can't tell how they are any different than Xiltera.

Maybe an FPGA company can provide us large islands of clockless logic and the tools to build something useful with them?

How about useful internal hard macrofunctions beyond Multipliers, DSPs and FIFOs?  Large CAMs, barrel shifters, and other things that take up a large chunk of LUT/routing resources come to mind...

 

KarlS01
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Re: Speaking of Gate Arrays...
KarlS01   4/23/2014 10:04:03 AM
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@betajet: Keeping the bit stream/configuration details secret just adds to speculation that there is some hidden magic.  The  real problem is that every flip-flop and every LUT connection has at least 2 SRam cells in/out.  Every connection between vertical and horizontal wwire is another cell.  The "wiring delay" has caused Xilinx to launch a new design tool suite.  The wiring delays swamps the circuit delays.

Horizontal micro-code has been used for DSP successfully and can be used for all controls.  Block memories with a few LUTs can be used for true programmable control logic without all the wiring and timing closure effort in the current methodology.  The access time for the block memory and LUTs is independent of the logic function beibg evaluated unlike gates where everything more complex than and or or requires more than 1 level.


Only the primitive peripheral logic needs to be discrete FFs and LUTs because of the unigue interfaces.

alex_m1
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Re: EE Time Recent Survey
alex_m1   4/23/2014 10:35:39 AM
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Or_bach, Thanks for posting ths.Very interesting.


At this efficiency level, fpga fabrics might start to finally be a standard part of microprocessors. Than we'll probably have fpga micros running on the cloud , and a lot of innovation.

Waiting to see how this will unfold.

 

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