TSMC's recent symposium in San Jose described a broad family of 2.5-D and 3-D ICs that exceeded my expectations. The company presented its work on chip stacks as one part of a broad overview of its technology portfolio for a North American market that makes up 74% of its foundry business.
The foundry giant currently offers four versions of its 28nm process, a 20nm planar technology, and is ramping up a 16nm FinFET process, said Jack Sun, TSMC's chief technology officer. It will offer a 16FF+ process before July that is GDS compatible with the current 16FF and sports 16% to 18% faster data rates and lower leakage, he said.
[Editors note: Competitors Samsung and Globalfoundries recently announced an early version of a 14nm ramping this year with plans for an enhanced version ramping in 2015.]
Looking further down the road map, Sun said TSMC plans a 10nm FinFET technology, which will be 2.2 times denser than the 16nm node. It also expects to offer risk production of a 7nm FinFET process in 2017. The foundry will spend $10 billion on capital equipment this year, the same capex as 2013.
In chip stacks, TSMC has developed low cost packaging alternatives in addition to its well known Chip on Wafer on Substrate (CoWoS) technology. They aim to serve a wide range of applications that could make 2.5-D/3-D packaging technology a strong third leg of the foundry's capabilities.
TSMC positioned CoWoS as a high-end process both in capabilities and cost. It offers up to 4,000 pins and allows interposers of up to 832mm2 using a 32 x 26mm reticle size.
By contrast, TSMC's next offering -- called an Integrated Fan Out Wafer-level Package (InFO-WLP) -- eliminates the costly substrate, streamlines manufacturing, but supports fewer pins and a smaller interposer area. It will start risk production before the end of the year, said Doug Yu, a senior director for chip stacks at TSMC.
In addition, an InFO PoP configuration will enable stacking a wire-bonded multi-die package on top of an InFO-WLP. It provides a thermally simpler design for applications that can tolerate additional package height. At the low end, a 2.5-D technology TSMC called Wafer-level Chip Scale Package will support devices with up to 800 pins.
As an example of a full 3-D IC design, Yu showed a package with a logic die and one to four Micron DRAMs, stacked vertically and connected using the Wide I/O standard. He hinted that there is room to further shrinking of the current 40nm pitch on the chip's through silicon vias.
This range of offerings could get chip stacks out of the chicken-and-egg phase where it has been stuck with suppliers and users waiting for each other to enable commercial products.