Verifying a modern ASIC/ASSP/SoC design is mind-boggling complicated. OneSpin's Quantify & Observation Coverage can significantly increase your verification confidence.
Are you having problems verifying your ASIC, ASSP, and SoC designs? Are you planning on attending the Design Automation Conference (DAC) this year? If you answered "yes" to both of these questions, then one company that would be well worth your time to visit is OneSpin Solutions. You will find the guys and gals from OneSpin hanging out at Booth #1219 (tell them "Max says Hi").
The reason I mention this here is that I've long had an interest in the verification of integrated circuit (IC) designs. When I started out designing my first ASIC in 1980, verification consisted of a bunch of your peers pouring over your hand-drawn, gate-level schematics while you explained what the various functional blocks were intended to do and how they performed their magic. If everyone said, "Well, that looks like it should work," then you were having a good day indeed.
Things have gotten mind-bogglingly more complex since then. Simply eyeballing a design is not going to "cut the mustard." In fact, even with all of the tools at our disposal, ensuring an IC design has been effectively tested during the verification process prior to fabrication remains a significant issue. This is made worse by an inability to effectively measure verification progress. Various verification coverage techniques have been employed for this task, but they all exhibit certain drawbacks (all of this is explained in excruciating detail in a whitepaper that's available from OneSpin's website).
Earlier this year at DVCon, the folks at OneSpin -- who are specialists in assertion-based verification (ABV) and formal equivalence checking solutions -- announced their new Quantify solution.
Quantify leverages something called Observation Coverage, a formal‐based approach to coverage measurement that has been proven on real-world designs to significantly increase verification confidence. Quantify's analysis can also pinpoint unreachable, redundant, or dead code, along with over-constrained design areas, and located and identify simulation coverage issues.
I hear that Quantify is going to be prominently featured in OneSpin's booth at DAC this year, so if you are in any way involved in the design and verification of ASICs, ASSP, and SoCs, then -- once again -- I suggest to amble over to their booth and say "Hi." Alternatively, if you aren't fortunate enough to be attending DAC (sad face), then you can discover more about Quantify and Observation Coverage by clicking here.
— Max Maxfield, Editor of All Things Fun & Interesting