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28nm FD-SOI: Samsung & ST's Major Opportunity

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AKH0
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Re: 28nm FD-SOI
AKH0   7/30/2014 1:18:40 PM
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Dear Sang Kim,

I am afraid you have mixed up many things. PDSOI has been in production at IBM down to 22nm. It has served IBM and other companies (AMD, Freescale, Sony, Nintendo, and Microsoft to name a few) for several generatios. So, unlike what you claim it is actually scalable. Even "the one time thing" long channel devices (180nm node) are being manufactured at a handful of foundries and are powering RF parts of nearly 50% of cell phones!

Samsung reported their 20nm bulk planar at IEDM 2011 (6 months before Intel's 22nm) and at smaller gate length, gate pitch (80nm vs 90nm) and metal pitch (64nm vs 80nm). Contrary to what you say, leakage was ok, down to 1nA/um for nominal gate length. TSMC also developed their 20nm node, and although they did not report device performance in public, customers like Qualcomm have already announced their product shipment plan. So, yes bulk planar is also scalable.

I cannot speak for ST or Samsung, but what I have seen in their announcement is that they are commited in offering 28FDSOI as a foundry service and that is happening even if you are not convinced.

With all respect, I would suggest that you through away anything you have heard about device physics, mobilit, etc and start afresh. There is no mobility degradation due to the prsence of back oxide interface. Quantum effects are not a monster to be afraid of. They are in play in any device and people have been accounting for those for many years. Those publications that reported mobility degradation in thin channel FDSOI only showed a modets 10-15% degradation in peak mobility down to any channel thickness of interest. Still those mobility numbers are almost 3X higher than typical numbers you get in the prsennce of high-k! So, the back interface is not a concern, certainly not at 5-7nm  that is used in any FDSOI technology.

28FDSOI has already showed performance advantage at circuit level over 28nm bulk. Otherwise why would Samsung invest in it?

The "end of roadmap" and technology scaling has nothing to do with the gate length. A 3nm node does not have a 3nm gate length, the same way that Intel's 22nm has a gate length of 35nm. All you need for the gate length is that it fits the gate pitch. That's why practically it has been not scaled since 65nm node. At some point you need to start scaling the gate length but cerytainly no one in right mind would go less than about 15nm. After that there are several possibilities. One is monolithic stacking of 2 or more transistor layers. The other is to use vertical channel devices to decouple gate length from gate pitch. Both of these have been practiced in NAND flash and there is no reason they cannot be used in logic. Although logic does not enjoy the uniform layout that memory has.  So there is no technology limitation that you want to solve with a FinFET that is "scalable to the end of roadmap". It all boils down to whether you can do any of these cost effectively. The major problem in advanced nodes is not the choice of transistor, it's how to make three contacts to each transistor. At 10nm you need 8 mask levels just to get from the transistor to M1 (which is another 3 masks to print). How does the choice of FinFET vs FDSOI affect this esclataing cost?

 

  

michigan0
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Re: 28nm FD-SOI
michigan0   7/30/2014 3:11:35 AM
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Sang Kim

 

IBM invented PDSOI, FDSOI and ET(extremely thin) SOI over

a decade ago. But PDSOI with a gate length of hundred 

micron meters was only manufactured but not today because 

PDSOI was not scalerable. It was just one time thing. You say 

"Samsung and others made 20nm bulk planar and showed their

results." What  are their results? The results are short channel 

effects or unable  to suppress the transistor leakage current. 

TSMC is said to manufacture 16nm FinFET this year or early 

2015, not 20nm bulk this year. You say that FDSOI products 

have already made by ST. and  Samsung a member of ST 

alliance is now committed to offer 28nm FDSOI to the public? 

That will not happen because  for 28nm FDSOI a 7nm thin SOI 

channel thickness is required. However, transistor performance 

becomes significantly degraded due to the transistor mobility 

degradation because of scattering of charge carriers at the top 

gate oxide surface and at the bottom SOI surface in the 7nm 

thin SOI channel. As a result, even if the 28nm FDSOI were 

manufactured today, it wouldn't be superior to the 28nm bulk 

in terms of the transistorperformance and manufacturing costs 

due to higher SOI wafer costs. The keypoint here is that the 

volume manufacturing of 28nm FDSOI was put on hold not 

because customer did not demands, but the poor FDSOI 

performance. These are the major reasons why 28nm FDSOI is 

not manufactured today. Based on Intel 14nm FinFET 

announcement, Origan fab is manufacturing 14nm FinFET in low 

volume, but not yet in huge Arizona fab that was built solely for 

14nm FinFET production. Surely there may be some delays.But 

Intel will be the First for mass production of 14nm FinFET just as 

done for 22nmFinFET. Yes, there is "end of roadmap". The end  

of road map is determined by device physics, not by the 

financial sense. 5nm channel length or gate length, Lg will be 

the end of roadmap or the end of transistor scaling because for 

3nm Lg the quantum mechanical confinement of charge carriers 

occurs. It means that electron and holes don't behave like

particles any more, instead behaving like waves in the 3nm Lg. 

As a result, the particle based classical Maxwell-Boltzmann 

statistics are no longer applicable, instead subjected to the 

quantum mechanical Heisenberg uncertainty,meaning large 

variabilities in the transistor electrical transfer characteristics 

such as Vt(increase), DIBL, Id/Vg and Id/Vd....etc. Intel FinFET

will be extended to the end of roadmap.





AKH0
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Re: 28nm FD-SOI
AKH0   7/26/2014 1:25:48 AM
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IBM's 22nm which is used for power8 is PDSOI, which is very similar to bulk planar in terms of scaling and in fact uses a gate length shorter than Intel's 22nm FinFET. Samsung and others made 20nm bulk planar and showed their results. ISDA's 20nm was shown in at VLSI 2012. TSMC is said to ship 20nm parts this year. The problem with 20nm was not scalability, it was cost. For your information foundry's 20nm uses 64nm metal pitch vs Intel's 80nm. Which means foundry is offering a denser technology, which of course comes at the cost of double patterning. FDSOI products have already made by ST, see for example NovaThor demo in early 2013 that clearly showed SOC benefit. Samsung is now committed to offer 28FDSOI to the public. I do not understand your repeated comment about 28nm bulk planar being in high volume for several years as a drawback of FDSOI. Yes, 28nm has been in production for several years, but it didn't come with all bells and whistles at the beginning. The first products used poly SiON gate stack and no strain element to keep cost down. Overtime several versions of the technology with different cost-performance trade offs were offered. They are put into volume manufacturing when fabless companies demand a certain performance and are willing to pay for that extra cost. 28FDSOI is no exception to this. Volume manufacturing was put on hold because customers did not demand. BTW, Intel's 14nm FinFET is not in manufacturing yet and there has been multiple delays. And there is no such thing as "end of roadmap". Technology is scaled as long as it makes financially sense to do so. Whether it's being conventional scaling of the transistor, being stacking in 3D, or a completely new technology the same way BJT was replaced by MOSFET logic.

michigan0
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Re: 28nm FD-SOI
michigan0   7/26/2014 12:37:42 AM
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Sang Kim

 

The 28nm planar bulk has retrograde and halos as you pointed 

out, but ends at the 28nm node. FDSOI is worse because 

FDSOI is not manufactured at any technology node yet as I

pointed out in my original post. Intel, IBM, TSMC and others 

attempted to extend the planar bulk to the 22nm node, but 

were not successful because of the short channel effect or 

unable to suppress transistor leakage current. Intel finally 

developed its first FDFinFETs at 22nm, and its 14nm FinFETs

are in high volume manufactured today. FinFET technology  

can be extended to the end of roadmap.



AKH0
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Re: 28nm FD-SOI
AKH0   7/23/2014 7:06:20 PM
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No, the doping is not uniform in bulk planar! The well is retrograde (although not ideal) and there are halos. The whole point is that the well and halo doping will take care of leakage at the depth and gate takes care of it at the surface. I agree with you that the ideal supersteep retrograde will end up with high drain leakage, but that's not the case in FDSOI because drain is isolated from the substrate by the BOX.

BTW, your point about Vt being higher and more variable in a retrograde well is not correct either. In fact it's the other way around! Please see page 230 of Taur and Ning's text book. With retrograde well design Vt is lower than a uniformly doped well and in the extreme case independent of the well doping. This is in fact what SuVolta is promoting. Of course, with Vt being independent of the well doping you cannot use Vt adjust anymore and need to rely on body bias. What FDSOI does is simply making an ideal retrograde well possible and allowing the well doping to have either n+ or p+ polarity for either NFET or PFET witout fearing about drain leakage.

 

 

 

 

 

 

michigan0
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Re: 28nm FD-SOI
michigan0   7/23/2014 6:39:41 PM
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Sang Kim

 

28nm planar bulk that is in mass production today for several 

years has uniform doped substrate that provides a fixed Vt  

and fixed depletion depth determined by uniform substrate 

doping. In a bulk planar device with super steep retrograde 

well, Vt could be higher and variable, and the gate depletion  

is blocked by the well doping, not by current flow. The current 

doesn't flow in the well unless hot carrier effect. The current 

flows from source to drain. Furthermore, the drain electric

field will be significantly higher in the retrograde well. As a 

result, hot carrier induced device failure could be higher.

 

First, the planar FD-SOI is not manufactured at any technology

node yet. Why? The un-doped 28nm FD-SOI requires an ultra-thin SOI channel, for an example, a 7nm for 28nm FD-SOI. My 

question is how the ideal super steep retrograde process can

be implemented in the 7nm thin SOI channel? It appears that

the un-doped planar 28nm FD-SOI is stilll not manufacturable.




AKH0
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Re: 28nm FD-SOI
AKH0   7/22/2014 12:07:43 AM
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In a bulk planar device with super steep retrograde well, gate only needs to control the top portion of the substrate. Current flow is blocked at deeper locations by the well doping. Similarly in the planar FDSOI gate only needs to control current flow in the SOI layer, below that current is blocked by the BOX. You can imagine an ideal super steep retrograde well device as being to be equal to an FDSOI device with a BOX thickness of zero. Would you say such a device will suffer from pinch through?

michigan0
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Re: 28nm FD-SOI
michigan0   7/21/2014 8:29:49 PM
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Dear AKHO

 

Thanks for your comments 

 

Bulk planer device has shallow implant combined with retrograde 

deep implant to prevent punchthrough regard less Vg is on or off. 

What do you mean by top 10~20nm is depleted? Intel FinFETs 

also have PT implants. Here we are talking about un-doped 

FD-SOI.



AKH0
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Re: 28nm FD-SOI
AKH0   7/21/2014 4:51:07 PM
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Dear Sang Kim

At Vg=0, the channel is fully depleted, whether it is in a planar FDSOI or in a FinFET with reasonably low doping. Even in a bulk planar device the top 10-20nm is depleted. That doesn't mean a well-behaved device is in punchthrough wheter it being FDSOI/FinFET/or bulk planar. Your way of describing what seems to be physics is incorrect. I would recommend you consult a text book. Punchthrough happens when gate significantly loses control of the channel and high current folows independent of the gate voltage. This is certainly not the case in all the I-Vs that have been published for sub-30nm gate length FDSOI devices. Drain-induced barrier lowerin (DIBL) is of course inherent to any short channel devices and you CANNOT make it zero. In fact I will argue it does not makes sense to make it smaller than about 100mV/V either.

 

Your assumption of the gate length needed for a given technology is also incorrect. Gate length has nothing to do with the technology node (and it didn't in the past). At 28nm, FDSOI is using a gate length of 24nm, which is shorter than any alternative at the same node. At 14nm, gate length will be most likely 20-22 nm and so is at 10nm. All needed from gate length is that it fits the required gate pitch and the numbers I quoted above fit the bill perfectly.

Finally, the rule of thumb requirements of the channel thickness for a given gate length are just guidlines. Many other parameters such as gate stack, junction design and BOX thickness affect the electrostatic of the device. This is also the case in FinFET. No one needs 3nm SOI for 14nm FDSOI.

 

 

 

 

 

michigan0
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28nm FD-SOI
michigan0   7/13/2014 1:48:51 AM
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Sang kim

 

Handel Jones says 28nm FD-SOI is an alternate option 

for low leakage, high yields and high performance superior 

to 28nm bulk technology. Consequently, Samsung

can support low leakage products with its 28nm FD-SOI.

look at the real issues with FD-SOI. My first question is why 

28nm FD-SOI is still not manufactured today by major 

semiconductor companies because 28nm bulk is manufactured 

for several years by major semiconductor companies today 

such as Intel, TSMC, Samsung and others. 

 

In un-doped FD-SOI channel here, it is possible for drain depletion to extend with large Vdd(1V) to source without inversion. I call this effect punch-through. Therefore, punch-through failure can occur in un-doped FD-SOI. On the other hand, the drain induced barrier lowering or DIBL leakage current most likely occurs also in un-doped FD-SOI. In order to prevent such DIBL leakage current it is imperative to have an ultra thin SOI channel layer between source and drain so that the drain field can't easily penetrate the ultra thin SOI channel. How thin the ultra thin SOI thickness has to be in order to stop DIBL leakage current? It depends on the channel or gate length, Lg. For shorter Lg, a thinner SOI  channel is required. This is the most critical issue for FD-SOI.

 

For 28nm FD-SOI a 7nm thin SOI channel thickness is required to stop DIBL leakage current. However, the transistor performance becomes significantly degraded due to the transistor mobility degradation because of scattering of charge carriers at the top gate oxide surface and at the bottom SOI surface in the 7nm thin SOI channel. As a result, even if 28nm FD-SOI were manufactured today, it wouldn't be superior to 28nm bulk in terms of transistor performance and manufacturing costs due to significantly higher SOI wafer costs. These are the major reasons why the 28nm FD-SOI is not manufactured today.

The other major issue with FD-SOI is its scalerbility. For

20/22nm FD-SOI a 4~5nm SOI channel thickness is required

to stop DIBL leakage current thus further degrading transistor 

mobility. Furthermore, it is extremely difficult to control 4~5nm 

SOI channel thickness uniformly and reliably across 12 inch 

wafers in the manufacturing line. How thin SOI channel 

thickness is required for 14nm FD-SOI technology? 3nm! It 

appears that FD-SOI is not scalerble. 

 





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