Samsung Electronics has a major opportunity with its large wafer capacity to support low-leakage products with its 28 nm FD-SOI process.
The foundry-fabless industry has demonstrated excellent performance in ramping 28 nm HKMG (High-K Metal Gate) technology into high-volume production. Additionally, both gate-last and gate-first technologies are giving high yields and reliable products.
Intel has high-volume production of its 22 nm Tri-Gate products, and its feature dimensions do not require double patterning. The second-generation Haswell 22 nm processor is also demonstrating high performance as well as long battery lifetime.
The next logical technology node is 20 nm HKMG, and TSMC is projecting 20 nm will represent 10% of its 2014 revenues ($2.2 billion to $2.3 billion) and 20% of its fourth-quarter revenues ($1.10 billion to $1.15 billion). With the capacity of 60,000 wafers per month (WPM), the average price for 20 nm wafers in the fourth quarter at $1.1 billion will be around $6,000. This is a relatively large increase in pricing compared with 28 nm wafers, which sell at $4,500.00 to $5,000.00. If TSMC achieves its projection for 20 nm, the company will have 95% of the 20 nm foundry market in the fourth quarter 2014.
There are, however, challenges in controlling leakage and gaining high yields of application processors and modems that require low leakage. If 20 nm does not provide low leakage with cost penalties compared to 28 nm, an alternate option is 28 nm FD-SOI. The wafer cost of 28 nm FD-SOI is comparable to 28 nm bulk CMOS, with performance potentially being 15% superior to 20 nm bulk CMOS.
Consequently, Samsung Electronics has a major opportunity with its large wafer capacity to support low-leakage products with its 28 nm FD-SOI process. Cadence Design Systems, Synopsys, and Mentor Graphics are all supporting the FD-SOI ecosystem, and the transition from 28 nm bulk HKMG to FD-SOI should be inexpensive.
16/14 nm 3D technology status
Intel, TSMC, Samsung, and Globalfoundries are trying to ramp their 3D structures. Intel planned to have the initial volume production of its 14 nm Tri-Gate structure in the fourth quarter of 2013, but low yields postponed this ramp-up.
A number of fabless companies will tape out their 16/14 FinFET product designs in the third quarter of 2014 with high-volume production planned for the second or third quarter of 2015.
Tens of billions of dollars are being committed by the semiconductor industry to have volume production of FinFETs in the next 12 to 18 months. What is the probability of this happening? And is the next-generation FD-SOI (called 14 nm by STMicroelectronics) a better option for mobile applications, which are the key driver for high-volume wafers?
The cost to manufacture a 16/14 nm FinFET wafer is approximately $4,000 at the high-volume stage, and with a gross profit margin of 45%, the selling price is around $7,270. The key issue is whether high systemic and parametric yields can be obtained from the initial designs. Based on an assessment of many variables, the probability of this occurring is very low.
FinFETs will happen, but there will be a learning process, and multiple design interactions will need to occur.
With this scenario, Samsung's adoption of FD-SOI and implementation of shrinkages are very astute decisions. If its 14 nm FinFETs ramp up as expected, Samsung's competitive position will be very strong, and if there is a delay in this ramp-up, Samsung has an alternate solution.
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