Today's designers need to seek next-generation development tools built from the ground up to address productivity bottlenecks in system-level integration and implementation.
The popularity and increasing capability of programmable devices and systems has enabled a new era of innovation and efficiency for designers in a wide range of industries. But with this progress comes new challenges -- challenges that must be addressed if the full potential of the emerging All Programmable era is to be realized.
Like all IC designers, design teams in the programmable world are constantly looking to achieve new levels of systems integration, increased system performance, lower BOM cost, and total system power reduction -- all against the backdrop of the relentless need to accelerate design productivity so they can get their innovations to market quickly. As chip complexity increases, new challenges appear, and thus more innovative approaches to design are required, both from the tools and the methodologies that enable them.
This is a delicate balancing act for tool providers and users: State-of-the-art algorithms, capabilities, and features must drive tool innovation, but industry standards and legacy environments must also be considered. The ideal is that all designers -- from those who require a highly automated, pushbutton flow to those who are extremely hands on -- will be able to design even the largest devices far faster and more effectively than before, while working in a state-of-the-industry EDA highly integrated environment that retains a familiar, intuitive look and feel.
With this in mind, here's a check list of "must haves" when considering some key features and best-practices that design teams should look to incorporate in order to achieve faster time to market (TTM).
Address the most pressing design challenges
With most designs, schedules are paramount, and the development environment must address this. Designers face a number of integration bottlenecks, including integrating algorithmic C/C++ and register-transfer level (RTL) IP; mixing DSP, embedded, connectivity, and logic domains; verifying blocks and "systems"; and reusing internal legacy designs and IP. They also face several implementation bottlenecks, including hierarchical chip planning and partitioning, "timing" closure, late ECOs, and the rippling effects of design changes. Designers need a tool suite that can address all these bottlenecks and empower them to take full advantage of the system integration capabilities of next-generation All Programmable devices.
Predictable design cycles with a design methodology
A design team can have access to the most advanced silicon in the world and the greatest tools in the world, but if the group doesn't establish a solid methodology, it's difficult to deliver products at the right time and turn that rollout into business success. A good design methodology not only cuts down design time to allow teams to deliver quality products on deadline, but it also allows them to do so in a predictable and repeatable manner -- a key to long-term business success. That said, methodologies must constantly evolve to take advantage of advances in silicon and design tools.
To become even more productive and successful in rolling out next-generation innovations, designers should seek best-practices from industry experts and distill these practices into a potent methodology that will speed the way for design teams to predictable success. These practices should cover all aspects of board planning, design creation, verification, design implementation and timing closure, programming, and hardware debug.
For example, to address predictable design cycles, Xilinx has published a free methodology manual. The UltraFast Methodology Guide for the Vivado Design Suite (UG949) covers an entire methodology, from board selection and RTL design verification to implementation and final debug. The document includes a comprehensive checklist designed to guide engineers throughout the design flow and leverage best-practices.
The UltraFast Design Methodology's main theme is to bring design closure to the front end of the design flow, where the impact on quality of results is greater (see Figure 1). In this way, design teams can rapidly converge on a correct-by-construction design. If an informed decision is made earlier in the flow levels, one can eliminate much longer cycles in the implementation phases.
Achieving closure at the beginning of the flow dramatically improves the quality of results and cuts design time.
With traditional tools, designers can discover issues only at the end of the process on the fully implemented design. If the design doesn't function as expected or timing closure is not achievable, the only choice is to backtrack to initial design steps, and there is little clue as to what caused the problem, so the team will incur many long iterative loops. The solution is to leverage a design methodology and a design tool suite that utilize a shared scalable data model that provides visibility into key design metrics (such as timing, power, resource utilization, and routing congestion) much earlier in the design process. The result of this combination is to enable design teams to accelerate productivity and repeatedly deliver designs to shorter, predictable schedules and thus deliver products to market sooner.
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