For phase change memory (PCM) watchers, VLSI Symposium 2014 in Honolulu, June 9 through 13, will offer fewer than five papers, while emerging non-volatile (NV) memory ReRAM/RRAM and MRAM get the lion's share of the formal papers. In fact, two sessions of the symposium are devoted to RRAM/ReRAM.
Of particular interest are the two PCM papers from the joint Macronix International and IBM T.J. Watson Research Center project. The first paper (11.1) is titled "A Double-Density Dual-Mode Phase Change Memory Using a Novel Background Storage Scheme," and it offers a new approach to multi-level cell (MLC) PCM.
In the past IBM, Zurich, has offered a solution to the drift problem that limits the use of PCM in an MLC mode. This new approach to multi-level is different because it allows each PCM cell to operate concurrently in two modes: foreground and background. More importantly, each cell has a bit capacity that is the product of the number of bits in the foreground and background modes. In the VLSI 2014 paper, a 4-bit per cell will be presented, the equivalent of 16 levels. It is conceivable that such a memory could operate in a multi-tasking role serving two separate applications.
The authors describe the way they achieve the multiple states as “stressing the memory cell with current that can shift the threshold for reset switching.” It would appear that the two normal high and low resistance states associated with a single-bit PCM cell can be further modulated. However, what is remarkable is a method has been found where the background state of the R-I characteristics is remembered when the device is switched between its more conventional high and low resistance foreground states.
While we wait for the publication of the paper, and the detail of the way in which the “stress” is applied, one can speculate how such a dual-role operation might possibly be achieved and some of the problems that would need to be overcome. In Figure 1, for the purposes of discussion I have illustrated the speculative I-V characteristics of a PCM operating as a 3-bit per cell in foreground and background mode. The red and green data levels are foreground data while the black dots and associated I-V curves are the background.
Ideally, it would be desirable to find a pulse sequence that can be applied to the cell without a pre-read and latch requirement. It might be the “stress” that the authors describe is a way of causing the memory to always retain some structure-based knowledge of its initial foreground data state.
A suggested way in which such a device might operate for writing foreground data is as follows. Start with a cell in its 1(01) that is to be written to its 0(01)state, i.e., a change of foreground data from 1 to 0. Apply a “stress” pulse followed by a series of four pulses that are each sufficient in reset current amplitude to reset the device from each of its foreground states. Once the device has reset, the remainder of the pulses in the sequence are incapable (insufficient voltage) of having any further effect, so they will be ignored. In the example, 1(01)-to-0(01), the second pulse in the sequence will reach the reset threshold and effect the reset. In each case, the amplitude of the reset pulse is only sufficient to reset the cell to a resistance and threshold voltage value proportionally related to its position in the sequence. The pre-stress pulse conditions the cell so single pulse reset discrimination is possible.
What if the device is in the high resistance (0 data) foreground state? In that case, a similar write “1” pulse sequence will be applied. Each pulse will be of increasing voltage amplitude but only sourced with sufficient current to set the device. If the write 1 pulse sequence is applied to a device already in the logic 1, then a pre-read would be one solution that would avoid over-writing problems.
For writing background data, the problem is a little more difficult and will most likely need to involve a two-step process. Figure 2 is a suggested means of writing background data. Initially pre-read, if the foreground is in the 1 state; then apply the reset sequence, which will carry the background data to the 0 foreground (blue line) state; then apply a single set pulse (orange line) to achieve the desired set background state. The upper curves of Figure 2 (a) and 2(b) are for transitions 1(00) to 1(11) and 1(11) to 1(00) respectively.
For transition within the 0 state, apply the pulse sequence this time with a current source that will write the desired set state. Then apply the reset pulse sequence. Figure 2 (c) and (d) illustrate the background data transitions of 0(00) to 0(11) and 0(11) to 0(00) respectively.
That speculation does not represent anything new and could be achieved with some clever circuit design with existing PCM devices, assuming that sufficient number of discrete levels can be obtained. For the 4-bit cell that will be reported in the IBM paper, and using the speculative approach illustrated here, some 16 discrete resistance levels would be required.
The authors of IBM's double density memory paper must have found some other way to get to the same end point. Clearly, the role of stressing must be more than just thermal. It will be interesting to see how the double-density approach deals with the problem of drift and many of the other outstanding PCM problems. It looks as though this paper may be the PCM highlight of VLSI 2014.
The second PCM paper (11.2) from the IBM-Macronix project is titled "Towards the Integration of both ROM and RAM Functions Phase Change Memory Cells on a Single Die for System-On-Chip (SOC) Applications." This paper will address the problem of integrating different memory functions on the same chip.
The team claims to have discovered a means of changing the characteristics of a PCM memory from RAM-like to ROM-like, that is fast write/erase or long data retention. If the title of the paper can be taken literally, meaning one-time programmable ROM rather that a long retention time re-writeable PCM, then one is tempted to ask: What's new? It has always been possible to change a PCM into a ROM by operating it as a PROM or even an anti-fuse by over-driving the cell.
The dual-role memory effect is not, as might be expected, to be obtained by some complex changes in active material composition or changing the write/erase conditions; it uses the same active material. The change is of the form of the dielectric cap that covers the PCM cell. The pre-Symposium preliminary information indicates that by using a low temperature silicon nitride capping material, the RAM-like memory characteristics are obtained, with claimed write times of 20 ns. With the silicon nitride capping material formed at high temperature, the data retention time is greater than 400 years at 85°C.
Continuing in our speculative vein, without detailed knowledge of the memory cell structure, this raises a number of possibilities as to the source of the effect. IBM already has some patent coverage in the area of memory structures that apply strain to phase-change material. It would be expected that that silicon nitride films formed at different temperatures would be under different levels of strain as well as having different densities, different thermal conductivities, and coefficients of thermal expansion.
There is also a possibility that these new devices rely on some of the earlier work from the IBM/Macronix team. In that work, complex electrode structures and thermal barrier layers were used to reduce reset current densities, reduce thermal losses, and improve the efficiency of the write set/reset operation.
The solution must rest with the physical close coupling of the dielectric cap with the active material, with considerations of strain, and then, less likely, some interaction of the silicon nitride with the amorphous memory material.
The so-called "cap of modern PCM structures" is illustrated in Figure 3, where the silicon nitride almost completely envelops the active material, creating what might be considered a nano pressure flask.
We know that the application of pressure can change the electrical and structural characteristics of amorphous material. In fact, IBM also has some patent coverage in this area (US20130001499 A1). So it is likely the silicon nitride deposited at two different temperatures provides the different levels of strain and pressure on the amorphous memory material, resulting in the two difference performance characteristics.
PCM watchers will have to wait for the formal presentation at VLSI2014 for the answers to that question and the reality of the RAM/ROM structure and performance, certainly something for us to look forward to.
A third PCM-related paper of note from Stanford University (15.4) is "A 1TnR Array Architecture using a One-Dimensional Selection Device." It bridges the gap between what might be the future, of electronic devices constructed using carbon nanotubes in the form of a carbon nanotube transistor, and links it to the PCM to create what is described as a “1TnR” PCM cell.
It is claimed the 1TnR architecture enables array sizes that approach that for a 1T1R structure while achieving device density similar to a 1R array. It is claimed the carbon nanotube FET (CnFET) device has good electrical characteristics with ultra-low leakage current (< 1 pA) and large ON/OFF ratio (> 1M) and is capable of operating at high current densities to serve as a 1D selector. The 1TnR PCM cells are reported to show endurance of more than 100 cycles with uniform resistance values and high ON-to-OFF ratios, resulting from the small contact area (~ several nm x nm). What are described as “ultra-low” set and reset currents of < 1 μA are also achieved. The authors believe the same 1TnR concept will be applicable to metal oxide RRAM and CbRAM and may offer a practical tradeoff between device density and performance, thereby providing a second bridge.