Finding the right materials will be one of the keys to delivering chips from 5 to 10 nm, say researchers who will present at SemiCon West in July.
The semiconductor industry must select from a wide variety of materials for substrates, channels, gates, and contacts as it scales transistors from 10 nm to 7 nm and beyond.
"For logic [at 14 nm and 10 nm], the architectures are defined," said Raj Jammy, general manager of the semiconductor group at Intermolecular Inc. and one of several scheduled presenters on the topic at Semicon West in July. "In most cases, they are FinFETs, but there is also an alternate option, which is fully-depleted SOI."
For both 10 nm and 7 nm, he thinks that high-k metal gates will tend to be dominant, but the real challenge will be the channel itself. At 10 nm, germanium (Ge) will likely be one of the channel materials. "But the moment you add Ge, a whole range of questions open up."
Within the 300 mm development line at the State University of New York College of Nanoscale Science and Engineering, several alternate device architectures are already under development. "Silicon nanowire devices have been developed on 300 mm wafers and evaluated for radiation hardened applications," said Christopher Borst, associate professor of nanoengineering at SUNY CNSE and another scheduled Semicon West speaker.
In parallel with the silicon nanowire effort, SUNY CNSE researchers have a development focus on materials beyond Si and are working with industrial and research partners.
"III-V layers are being evaluated as channel materials for next-generation devices," said Borst. "We are committed to developing modules for III-V gate stack, contact, and source-drain engineering that are compliant with environmental guidelines, while driving to sub-10 nm device performance targets."
SUNY CNSE is also involved in R&D on replacing silicon devices with graphene or another 2D monolayer material. "Graphene is currently the front-running disruptive solution for next-generation device architectures," Borst said. "We are working on the growth, device design, and integrated module development for these layers with a view to their subsequent introduction into mainstream processing."
So far, researchers have had success growing graphene and transferring it to 300 mm wafer substrates for repeatable processing.
Researchers expect semiconductors will adopt many new materials as they advance from the 16-11 nm node (left) to the 5 nm node (right).
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