Micron Technology Inc. has outlined its plans for participation in the upcoming 2014 Symposia on VLSI Technology and Circuits scheduled for June 9 through June 13.
With executive panel appearances, the Micron research and development team will focus its presentations at the conference on the integration of silicon photonics in bulk CMOS and copper resistive random access memory (ReRAM) for storage class memory applications.
Micron states the copper ReRAM cell for storage class memory targets hybrid memory systems that incorporate storage class memory as non-volatile cache or DRAM data backup. This they claim is expected to bolster system efficiency and reduce costs (since storage class memory promises higher density than DRAM cache and higher speed than the storage control module). In its announcement, Micron says the presentation will introduce a ReRAM cell technology meeting the storage class memory performance specifications for a 16 Gigabit ReRAM with 200 Megabyte per second write and 1 Gigabyte per second read speeds. This technology is being developed in close collaboration with Micron's research partner Sony Corporation.
A valuable by-product of the development of the 16 Gbit ReRAM is it looks as though it will be able serve as a useful 16 Gb test bed at the 27nm node for laboratory claims of all manner of ReRAM/RRAM technologies that require either bi-directional or uni-directional current flow for write/erase. The solution to the problem of matrix isolation for bi-directional memory devices is a very noteworthy feature of the Micron/Sony 16 Gb memory program.
I hope that this latest introduction includes some information on the planned date for a product introduction and more details of other performance of the 16 Gb device beyond the claimed interface performance.
Mark Bauer, director of architecture for the Micron NAND Solutions Group, will serve as a panelist on June 12 discussing "Lessons and Challenges for Future Mixed-Signal, RF and Memory Circuits." Hopefully, he will include the lessons learned from the recent abortive foray into phase change memory (PCM) development, product introduction, and product withdrawal.
Other Micron team contributions at VLSI2014 will come from Micron's Scott DeBoer, vice president of research and development, who will serve as a panelist on the Emerging Semiconductor Industry Trends and Implications session. While Ed Doller, vice president and chief memory systems architect, will speak June 11 at a circuits plenary session entitled "DataCenter 2020: Near-Memory Acceleration for Data-Oriented Applications."
The integration of silicon photonics in bulk CMOS presentation details Micron's research on the development of the first monolithic process flow integrating silicon photonics on operational bulk CMOS. The research demonstrates silicon photonics as a "More-than-Moore's Law" pathway to enable future high-performance memory applications. This effort is part of a larger project on building a complete photonic processor-memory system that includes research teams from Massachusetts Institute of Technology (MIT), University of Colorado Boulder, and University of California, Berkeley. The research was funded by the Defense Advanced Research Projects Agency.
The first step has to be the solution to high-speed photonic chip-to-chip communication, followed by an optical read/write memory. The latter is the real challenge for the future.