A look at the ReRAM and RRAM papers at this year's VLSI 2014 conference.
The ability to improve the performance of ReRAMs and RRAMs by engineering the shape and composition of the conducting filament for the low resistance state (LRS) of the memory cell received the close attention of a number VLSI 2014, Hawaii, papers. The presenters are seeking to improve performance and increase the understanding of ReRAM/RRAM operation. However, there does not yet appear to be one material or memory type that is a clear winner.
A team from Fudan University and the Semiconductor Manufacturing International Corp., Shanghai, , used a 128k-bit ReRAM memory array of bi-layer AlOx/WOx memory cells to evaluate all the possible (4) different combinations of set and reset pulse trains that either increased or decreased in amplitude and then introduced a new one. This new pulse sequence is called FS-DSUR (fast speed-down set up reset), where the pulses are merged together in a single stepped pulse. Removing the read verify between pulses saves both time and power. The resistance of the growing filament is monitored continually during set pulse steps, and the pulse, or pulse train, is terminated when the required resistance value is reached.
The interpretation is that set pulses reducing in amplitude create a parallel shaped filament, while a set pulse train increasing in amplitude creates a frustum conical shaped filament with the broadest part of the section in contact with the bottom electrode (see Figure 1).
The filament options not shown in Figure 1 are the incomplete cylindrical filament and the over SET conical filament; the latter can occur with both SET-up and SET-down type pulses.
One of the advantages of the step-down pulse (where a cylindrical filament is formed) is that a reset pulse of a given amplitude will create a wider gap in the filament and therefore a higher off-state resistance. This latest work reported that both versions of DSUR, steps and discrete pulses, were able to provide write/erase (W/E) endurance of 109 cycles with the new FS-DSUR marginally better. In all cases, a step-down reset offered no advantage. This work also discovered that there was a maximum in the individual step width, or pulse width, of 60nsecs in order to obtain the unverified 109 W/E cycle endurance.
IMEC, Belgium was well represented at VLSI 2014. One paper  used a TiN/Ta2O5/Ta memory structure and explored the relationship between the thickness of the tantalum (acting as a scavenger layer for oxygen when the device is formed) and its data retention properties.
A model to explain retention changes for both the reset and set state was developed (see Figure 2). It leads to the conclusion that retention is strongly related to the thickness of the upper electrode and its scavenging ability, rather than it is to the properties of the filament alone.
A thick upper Ta electrode of 30nm Ta/6nm Ta2O5 compromises the elevated temperature data retention in the high-resistance state (HRS), and not the LRS, while a thin upper electrode 10nm Ta/6nm Ta2O5 has the opposite effect.
In the LRS for a thick upper electrode there are two directions in which oxygen ions can move (small red arrows) while for a thin electrode there is only one (see Figure 2). The result is a large change in resistance (data retention) for the LRS with thin electrodes when subjected to thermal stress. For the thick upper electrode, it is the HRS state it is most effected by thermal stressing because there is a higher density of oxygen vacancies close the lower electrode that can move towards the higher resistance region of the filament and reduce its resistance.
This means that it should be possible to find an upper electrode thickness that provides the optimal performance in both respects for data retention. The retention tests were carried out at temperatures of 250deg.C for 30 days. With 3nm Ta2O5, it was claimed that forming voltages and operating voltages of < 2 Volts are possible with associated write current of 50uA and write times of 5 to 10ns.
The formation of the RRAM scavenging electrode was again the focus of the work of another team from IMEC, Belgium, , this time using a TiN/HfO/Hf/TiN structure where the Hf served as an oxygen scavenging layer by taking oxygen from the HfO film. Specifically, the effects investigated were on the thickness of the oxygen exchange layer (OEL) of doping the HfO film with 18% of Ti,Si and Al. The OEL is the key to the operation of the device, and it is formed during processing. It has never been clear as to the variables that influence the thickness of the OEL as it carries out its initial oxygen scavenging role. This paper provided at least one of the important variables, i.e. doping. The HfO2/Hf RRAM cell structure (see Figure 3 which is not to scale) consists of a 5nm oxide layer and a 10nm hafnium cap.
It was found that changes in SET/RESET voltages, endurance, data retention, and the optimal programming window result mainly from
the oxygen scavenging efficiency of Hf cap in the presence of the different dopants. Doping offers a means of controlling the formation and thickness of the OEL, which controls the RRAM switching characteristics and retention. Ti doping resulted in the widest OEL, followed by the more normal undoped HfO. Aluminum and silicon provided the thinnest OEL. The authors of the paper suggest that doping of the oxide layer may offer a route to designing RRAM for different applications.
Logic with memory
A group from the Low-power Electronics Association & Project (LEAP), Japan, , explored the possibility of combining memory with logic for what they described as non-volatile programmable logic (NPL) functions.
What is described as a complementary atom switch (CAS) is based on two copper filament memory devices in series with a control electrode at the mid-point (see Figure 4). The individual memory elements from the bottom electrode up have a copper electrode, AlTiO buffer layer, a polymer solid electrolyte (PSE), and a Ru alloy upper electrode.
The optimal composition of the buffer layer with 50% Ti prevents the
formation of a passivation layer of aluminum or titanium oxide forming on the surface of the buffer. This prevents the oxygen for the redox process from reaching the surface of the copper electrode, leaving metal particles at that surface which in turn act to limit set time. Minimizing the write time is essential if this device has to have any claims as a memory or logic device. By optimizing the buffer composition, write times of 10ns are claimed with the switching speed, starting at about 1 sec for 1.5volts and falling to 10ns at 2Volts for a value of 56mV/decade, with a write currents in the range 300 to 500 micro-Amps. The write/erase cycle endurance was reported as just over 1000 cycles, so clearly more work to be done in that respect. For evaluation, a 1Mb memory array was fabricated. Stress testing indicates a projected data retention of 10 years at 125 deg.C. One of the extremely important results from this work is a claim that the memory devices do not require forming, and the first switching event is the same as all subsequent switching events.
Slowly, a more complete understanding of the variables and details of the operation of RRAMs and filament formation in many different types of memory device and materials is becoming clearer. The fact that there appear to be so many promising RRAM and ReRAM technologies may be a problem as well as an opportunity.
My view is rather than promise what is needed, all of those throwing their proverbial hats into the ring should use the information they have to provide a memory cell design that could be monolithically integrated into a 8Gb memory array, for example, and define the performance. At the moment, it is this writer's view that it might be better if emerging NV memory focused not on mass memory and bit density but on providing memory designs and solutions for the single-chip embedded memory business. That is where it now appears there is an opportunity for game-changing memory success.
1. Fast Step-Down Set Algorithm of Resistive Switching Memory with Low Programming Energy and Significant Reliability Improvement, Y. Meng, X. Y. Xue, Y. L. Song, J. G. Yang, B. A. Chen, Y. Y. Lin*, ASIC and System State Key Laboratory, Fudan University, Shanghai, 201203, China; Q. T. Zou, R. Huang, J. G. Wu
Technology Development Center, Semiconductor Manufacturing International Corp., Shanghai, 201203, China.
2. Role of the Ta scavenger electrode in the excellent switching control and reliability of a
scalable low-current operated TiN\Ta2O5\Ta RRAM device,
L. Goux1*, A. Fantini1, A. Redolfi1, C.Y. Chen, F.F. Shi, R. Degraeve1, Y.Y. Chen1, T. Witters1, G. Groeseneken, M. Jurczak1
imec, Kapeldreef 75, B-3001 Leuven, Belgium; 2 KU Leuven, Belgium.
3. Tailoring switching and endurance / retention reliability characteristics of HfO2 / Hf RRAM with Ti, Al, Si dopants, Y. Y. Chen, R. Roelofs*, A. Redolfi, R. Degraeve, D. Crotti, A. Fantini, S. Clima, B. Govoreanu, M. Komura**, L. Goux, L. Zhang***, A. Belmonte****, Q. Xie*, J. Maes*, G. Pourtois and M. Jurczak
imec, Kapeldreef 75, B3001, Leuven, Belgium; *ASM international, Belgium; **Toshiba assignee in imec,***also with Dept. of Electrical Engineering (ESAT), KU Leuven, Belgium; ****also with Dept. of Physics & Astronomy, KU Leuven, Belgium.
4. A Fast and Low-Voltage Cu Complementary-Atom-Switch 1Mb Array with High-Temperature Retention, N. Banno, M.Tada, T. Sakamoto, M. Miyamura, K. Okamoto, N. Iguchi, T. Nohisa, and H. Hada
Low-power Electronics Association & Project (LEAP), West 7A, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan.