From the clues (there are at least four of them) hidden in the schematic above, what would you say are the most likely loads for the drains of transistors Q1 and Q2 connected to EdgeConn1 and EdgeConn2, respectively? Also, please describe what led you to your conclusions.
But 48V is a common telecommunications cupply voltage.....
Isn't it -48V?
I do agree that it appears to be switching two loads in anti phase. The outputs appear to have a belt and braces approach- it appears to be a zener for back emf protection, but also has some form of snubber. Perhaps that is some clue as to the load, but for the moment it escapes me.
The alarm circuit also gives some clues. Assuming the CMOS will switch state at 5 V the circuit looks for a smothed signal of above about 20V (assuming 400Hz) to trigger an alarm. But the alarm would not be open or closed circuit since a DC signal would not propogate across the capacitors C1/C3.
CR4 and CR6 in the alarm circuit would seem to imply the the signal could go negative. Are they merely good design practice or there for a real reason? And so perhaps CR8 and CR9 are more than back emf protection but aslo bypass for the transistor when (and if) the output signal is negative?
Diode CR2 and its unmarked partner in the other drive give directionality on the snubber, if it is indeed a snubber. There is a DC trickle current draw through R6 and R7, but what sort of device needs to have this low current to stay active?
The MOSFET drivers are not buffered so the output has no requirement for sharp edges.
Maybe it's my jet lag, but none of this leads me to any conclusion. I need to sleep on it.
Like Wnderer I think it's an inverter of sorts....arranged so there is no overlap on the Mosfets drive....so the load would probably be a transformer, centre tap primary, the outers connected to the transistors and the centre tap connected to the 48V supply. Who knows what voltage the secondary would be..??? 400 Hz is frequently used in aircraft systems, but I'm not sure what voltage (110V?) But 48V is a common telecommunications supply voltage.....
My guess is the circuit is a 400 Hz inverter. The load is a transformer. The 555 is generating 800 hz signal. That gets divided down by 2 by the flip-flops. The two transistors are run in sequence 10 00 01 00 10 00 01 00 ... The transistors are tied to the ends of the primary. Power goes to the center tap of the primary. The secondary has a 400Hz AC signal on it.
I'm looking forward to seeing the responses here -- in fact I'm just about to stroll over into the next bay and tell Ivan (the creator of the All About Batteries series) about this puzzle -- he's brilliant at this sort of thing.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.