Creating the highest performance and lowest power DDR4 and LPDDR4 memory intellectual property (IP) is an extremely competitive field, but the race is on.
The race is on to declare the fastest, highest performance, and lowest power DDR4 and LPDDR4 memory intellectual property (IP). This is a decidedly ultra-competitive field, since this particular IP is known to cover a wide variety of ASIC and SoC devices for many different applications and market segments. Chances are, if the device has an embedded processor, then it needs access to external DDR memory. A DDR subsystem, including the DDR controller, PHY, and I/O, manages the data traffic flowing to and from the embedded processor and external DDR memory -- a critically important role.
The importance of production-quality DDR4 and LPDDR4 cannot be understated. Many project teams are skipping LPDDR3 and implementing LPDDR4 for various reasons, but most believe they're getting greater gains in performance and lower power by jumping to LPDDR4. Even without the need for extra performance, some project teams are motivated to move to DDR4 for practical and cost-effective reasons. If they have a product with a life span of five years or more, they believe that DDR3 memory will eventually cost more than DDR4.
All of this makes a recent spate of announcements all the more interesting …
In April 2014, one supplier announced availability of models for a complete LPDDR4 IP solution for high-performance, low-power mobile SoC designs. It claims its PHY, controller, and verification IP will deliver close to 3,200 megabits per second (Mbit/s) speed when proven in silicon. It's the "when" that's unclear from the news release.
In May 2014, another supplier announced a DDR4 PHY IP built on TSMC's 16-nanometer (nm) FinFET process. This announcement further states that it should be scalable to support higher speed (3,200 Mbit/s) DDR memory components when they become available. The IP will target the server, network switching, and storage fabric markets, all of which require high-memory bandwidth.
Yet another supplier also announced in May the fastest DDR4 memory IP, clocking 2,800 Mbit/s in silicon for TSMC's 28HPM process technology using DDR components rated at 2,400 Mbit/s. This speed was achieved in silicon by relying on dynamic self-calibrating logic (DSCL), an adaptive technique that precisely and dynamically calibrates the DDR memory timing.
Later in May, this same supplier announced its LPDDR4 memory IP -- including the memory controller IP and PHY models -- for low-power, high-performance applications, including mobile and handheld products.
This supplier's initial test silicon for LPDDR4 is targeting performance of 3,200 Mbit/s, with plans to support speeds in excess of 4,200 Mbit/s as the design is refined for both 16nm FinFET and 28nm process technologies. Again, the company's patented DSCL and dynamic adaptive bit calibration (DABC) are cited as the reasons why it is able to deliver on performance, a small footprint, and minimized power consumption -- all absolutes for the consumer market.
Let's look at this more closely. While DDR memory IP is ubiquitous in SoCs, it can be a little troublesome when it comes to system yield and field reliability. If the DDR system does not work reliably, the product won't work.
DSCL provides a precise calibration of the DDR memory subsystem comprised of the SoC and DDR interface, package, board (or other substrate), and the DDR SDRAM components. Each system is uniquely different due to imperfections in the manufacturing process. Further, a system's operating point changes as it runs due to temperature or voltage fluctuations, both of which can alter critical DDR timing. DSCL automatically detects changes in the DDR operating point and automatically adjusts the DDR timing to track these changes. DSCL operates dynamically during system operation, which solves the fundamental problem of system yield and reliability.
DABC manages and dynamically corrects for intra-byte lane skew. Only one clock is assigned to each byte lane, and all bits ideally are aligned and arrive at the same time. That is a difficult-to-achieve design challenge. Without careful design, there is a noticeable skew between the data bits in the byte lane, impacting the quality and robustness of the DDR "eye," which are both critical to delivering a high-quality, highly-reliable DDR subsystem. DABC dynamically manages bit-to-bit skew within the byte lane by aligning bit timing to reduce skew greatly.
The need for DSCL and DABC goes up with higher speed and higher clocking requirements where the margins are much smaller. For these reasons, creating the highest performance and lowest power DDR4 and LPDDR4 memory intellectual property (IP) is an extremely competitive field, but the race is on. Who will be the winner is unclear, but I'm placing my win, place, or show bets on the supplier with the DSCL and DABC techniques.
About the author
Bob Smith is senior vice president of marketing and business development at Uniquify. He began his career in high technology as an analog design engineer working at Hewlett Packard.
Since that time, he has spent more than 30 years in various roles in marketing, business development, and executive management, primarily working with startup and early-stage companies. These companies include IKOS Systems, Synopsys, LogicVision, and Magma Design Automation. He was a member of the IPO teams that took Synopsys public in 1992 and Magma public in 2001. Smith received a BS in electrical engineering from the University of California at Davis and an MS in electrical engineering from Stanford University.