A couple of days ago, I posted this column in which I posed a puzzle involving the following circuit:
As I noted, these are a number of clues hidden in the schematic. From these clues, your mission was to describe the most likely loads for the drains of transistors Q1 and Q2 connected to EdgeConn1 and EdgeConn2, respectively.
Now, all will be revealed. Let's start by performing some simulations, and use the results to try to figure out what this circuit is all about.
Clue No. 1
The NE555 is wired as an 800Hz astable with a highly offset duty cycle. Its inverted output waveform, shown below, is at Pin 2 of the 4069 IC. The vertical scale is normalized to 1 for a 10-volt swing.
Clue No. 2
The D-type flip-flops and NAND gates produce the gate drive of heat-sunk power FETs Q1 and Q2 as shown below. Because the two flip-flop clocks are inverted, Q1 switches on the rising edge of the above clock and Q2 switches on the falling edge. The low duty cycle of the clock causes a brief interval where neither Q1 nor Q2 is on at the same time. The frequency is 400Hz, which is a standard power frequency (hint, hint).
Clue No. 3
Knowing that the main power input is 48 volts, let's assume the FETs are switching resistive loads that pull up to +48 volts. The resulting DC levels at the NAND 4011 inputs (pins 8 and 9) are generated by AC-coupled diode peak detector networks, but after startup transients stabilize the level is wrong for a CMOS gate with a Vdd of 10 volts. Not only is it too close to the switching threshold, but is always going to be seen as a logic 0 whether the FETs are switching or not.
Clue No. 4
To get the peak-detected DC level at the NAND inputs to a proper logic level of at least 7 volts, let's assume that the FETs' peak drain voltage is actually doubled or 96 volts. Now the NAND gets valid HI input logic levels, either of which will pull down to LO if either FET stops switching and gets stuck on (shorted) or off (open).
Yes, of course we all know that -- in the real world -- the NAND input clamp diodes would not allow the initial transient to rise above 10.5 volts, but the simulator doesn't know that.
Clue No. 5
The FETs are shunted by zener diodes, which clamp any positive spikes to 110 volts. They are also shunted by RCD networks that look suspiciously like snubbers.
From all of the clues above, can you now deduce the load?
The answer to life, the universe, and everything
Zener clamps and snubbers imply inductive loads. The FETs' on times do not overlap, so they probably have a common load. The alarm monitor NAND wants double the 48V supply voltage, and the frequency is a power standard 400Hz.
If you deduced that the FETs are connected to the ends of a center-tapped power transformer primary winding, you'd be absolutely right. Such a load most certainly would not be happy if both FETs were to be on simultaneously, and the push-pull drive causes the opposite ends of the winding to pivot about the 48 volts at the center tap. So when one side of the winding is pulled to ground by its FET turning on, the other end of the winding rises to 96 volts as shown in the simulation below.
Thanks to everyone who took part in solving this puzzler. Please post any comments and questions below. And if you have any suggestions for similar puzzles, please email them to Max Maxfield at email@example.com.