A light breeze was clearing the starry sky in Bangalore, India, on a warm early spring Friday evening. Down on earth, the weekend rush hour made the road traffic particularly dire for Ajay riding his motorbike to work.
The following Monday was the deadline for completing the system validation of a new system-on-chip (SoC) design upon which Ajay's employer was betting the future of the company. Ajay felt the entire world resting on his shoulders and he was distracted. Getting to his cubicle fast would put him on top -- or close to it -- in the queue to access the emulation design datacenter in Silicon Valley for the night runs. Immense verification processing power was one click away from his desktop.
This fictitious scenario is becoming reality for many design and verification engineers. It may remind some readers of the queue-up to use remote centralized simulation server farms. Yes, simulation farms have been effective for less complex designs. They are good for parallel jobs, typically regression test suites where each test involves only a few million clock cycles.
Well then, readers may wonder why emulation design datacenters are becoming so popular as opposed to something else. "Because of economy of scale" would be the simple answer.
First, let's recall a popular refrain: Semiconductor design is getting out of control due the incessant expansion of complexity in SoC designs, both in hardware and in embedded software. The bulk of the design work, consuming well in excess of 50% of resources in time and money, rests on the verification team, which is comprised of hardware designers and software engineers (lately, more software engineers than hardware designers).
This thorny state of affairs is pushing the electronic design automation (EDA) industry down the path to create more powerful and more sophisticated tools. The tools need to be faster and feature rich, as well as flexible and easier to use. Indubitably, EDA vendors are expected to "seamlessly" integrate existing and new tools to support an all-in-one ecosystem that can verify a SoC design from A-to-Z, and that's not an effortless endeavor.
Among the verification tools, today's hardware emulators are king and reign over the verification landscape, but not at a trivial cost. Compared with the old versions of a decade ago, a modern emulator is relatively easy to use. It can automatically map any design size in a matter of a few hours, and it offers 100% design visibility for thorough debugging.
With emulation, register transfer level (RTL) source code can be used as the system-level model. The emulator can process regression test suites in minutes instead of days, and it can execute embedded software in hours instead of weeks or even months. This is an important difference between emulation and simulation; simulators are not useful -- or even applicable -- for processing billion of cycles as required by the sequential nature of embedded software.
Through a transaction-based communication channel, a modern emulator can interface to a virtual environment, a capability that has opened up an entire new usage model for higher productivity. Designers can replace a physical target system that drives a design under test (DUT) via an in-circuit emulation interface with an equivalent virtual target system. A physical target system typically resides in a lab and includes a collection of computer peripherals, such as PCIe, USB, SATA, Ethernet, or multimedia. A virtual lab can be built and populated with equivalent virtual peripherals and then loaded in a host server connected to the emulator.
At the tip of the finger, the emulation environment can be reconfigured for any design from anywhere on the planet, increasing the utilization of the emulator and ultimately the productivity of the engineering team.
If loaded with enough resources, a modern emulator can be accessed 24/7 and shared among tens of concurrent users distributed on a vast territory covering multiple continents.
The combination of large capacity, multi-user capability, and remote access are at the foundation of emulation design datacenters. They have fairly widespread appeal because they are able to remotely support big groups of verification engineers and software developers worldwide and meet their daunting requirements.
It won't be long before a real-life Ajay is recounting his experiences at an industry event or in a technical contributed article. He will be able to boast about saving the day through the completion of a rigorous system validation of a new SoC design destined to make his company the semiconductor industry's darling. And Ajay will achieve this with the help of an emulation design datacenter.
About Lauro Rizzatti
Lauro Rizzatti is a verification and management consultant. He was formerly general manager of EVE-USA and its vice president of marketing before Synopsys' acquisition of EVE. Previously, he held positions in management, product marketing, technical marketing, and engineering. He can be reached at email@example.com.