Design Con 2015
Breaking News
Blog

The Risks & Rewards of Early Tapeout

View Comments: Newest First | Oldest First | Threaded View
<<   <   Page 2 / 2
Darren.Galpin
User Rank
Rookie
Re: Good reference
Darren.Galpin   7/23/2014 3:34:38 AM
NO RATINGS
cs20 is correct. You may be able to run much more on actual silicon, but the visibility for debug should something go wrong is awful, and only gets worse with the increasing amounts of IP and processor cores on silicon. And with increasing design complexity you have an increased number of possibilities of use cases, and who knows if you don't have access to customer code whether you've covered the use case they have in mind?

 

But we are discussing this from an engineering view point, whereas such decisions are often made much more on an economic view point. It costs a couple of million for a new mask set, so up front avoiding a respin saves me a fixed amount of money against saving a theoretical amount if I can catch a bug in silicon which may not be there. Economics will win out every time.

cs20
User Rank
Rookie
Good reference
cs20   7/22/2014 9:12:04 PM
It is a good reference for the team who want to do early tapeout.

The respin cost is too high today. Our target is "first time success" to save the cost and reduce TTM. Unfortunatly the respin is the reality. So our "reality" target is reduce the respin time and cost. The methods include: tapeout for partial respin and ECO; full verification to reduce bug founds in silicon sample; use a FPGA prototype to test in a "real world" and do HW/SW co-development.

<<   <   Page 2 / 2
Radio
NEXT UPCOMING BROADCAST
EE Times Senior Technical Editor Martin Rowe will interview EMC engineer Kenneth Wyatt.
Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll