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The Risks & Rewards of Early Tapeout

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cs20
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Good reference
cs20   7/22/2014 9:12:04 PM
It is a good reference for the team who want to do early tapeout.

The respin cost is too high today. Our target is "first time success" to save the cost and reduce TTM. Unfortunatly the respin is the reality. So our "reality" target is reduce the respin time and cost. The methods include: tapeout for partial respin and ECO; full verification to reduce bug founds in silicon sample; use a FPGA prototype to test in a "real world" and do HW/SW co-development.

Darren.Galpin
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Re: Good reference
Darren.Galpin   7/23/2014 3:34:38 AM
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cs20 is correct. You may be able to run much more on actual silicon, but the visibility for debug should something go wrong is awful, and only gets worse with the increasing amounts of IP and processor cores on silicon. And with increasing design complexity you have an increased number of possibilities of use cases, and who knows if you don't have access to customer code whether you've covered the use case they have in mind?

 

But we are discussing this from an engineering view point, whereas such decisions are often made much more on an economic view point. It costs a couple of million for a new mask set, so up front avoiding a respin saves me a fixed amount of money against saving a theoretical amount if I can catch a bug in silicon which may not be there. Economics will win out every time.

tommyma518
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Re: Good reference
tommyma518   7/23/2014 6:22:42 AM
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yes, i think so

MikeBartley
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Re: Good reference
MikeBartley   7/23/2014 9:20:17 AM
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Hi Darren

You're right - econmics should dominate the decision. However, TTM (time to market) is often a key issue in economics (imageine a new mobile phone missing its Christmas launch). So the fab cost might be justified on a TTM calculation

Mike

roman.wang
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Re: Good reference
roman.wang   7/23/2014 10:59:28 AM
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Good article.

 

Is it possible for verification team to iron out all the bugs before taping out within the tough project schedule?

No one could have confidence to say yes. the re-spin usually happens in most of team.

 

The verification team may take the silicon as the HW accelerator for re-spin. it may be too late for market.

 

So the early tape-out is a smart verificaiton but more $$ cost.

 

This should be a tradeoff between $$ and time-to-market. 

I guess the re-spin may miss the market and take more $$.

 

any thought?

Zavi_#1
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Great but expensive and unpredictable solution
Zavi_#1   7/23/2014 11:18:06 AM
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Firstly, how we define "early" tapeout? Which stage is early in the whole development cycle? That could be a different answer to different products and different companies.
Secondly, early tapeout could bring absolute benefits for verification. But  it may be confined in a narrow scope for corner bugs not normal bugs which can be caught easily by normal flow. Maybe accelation in mix-signal simulation and early development for bios, driver and software could be potential advantages. Tapeout is a hugh process and involves both frontend and backend efforts. We should take extra work for DE and PD into consideration when evaluating the ecnomical gains and losses.

RogerSabbagh
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Not a substitute for advanced verification methods
RogerSabbagh   7/23/2014 6:11:15 PM
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Mike,

Thanks for this succinct presentation of the trade-offs that should be considered when planning for early tapeout. The key point here is to have a plan for this!

I have been part of design teams that have done this before - sometimes called the two-pass approach. For the first pass, some of the design and/or verification tasks may be incomplete, but the chip is spun early to get system integration started. For any features that have been implemented but not fully tested, you have to assume they will be broken and make sure you can live without them with bypass/disable functions. This enables early system testing to iron out issues at that level and speed up s/w development and integration. All good stuff.

However, as your DAC panelists concluded, this is not a substitute for advanced verification methods! Just ask the guys designing complex FPGAs today. They can't use the "burn-and-learn" approach of the past anymore. H/W debug in the lab is much too resource intesive. A cost/benefit analysis will favor investing in advanced methods such as:
  • constrained random simulation with UVM
  • formal verification with formal apps
  • intelligent testbench automation
  • etc.

Roger

MikeBartley
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Re: Not a substitute for advanced verification methods
MikeBartley   7/24/2014 4:48:52 AM
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Thanks Roger

Your comparison with FPGA is very appropriate. We are also seeing the FPGA world move towards more simulation and less lab (although adoption of advanced techniques needs some persuasion!)

We encourage our customers to take a Requirements Driven Verification approach which helps to ensure a high level of confidence in the main user requirments and use cases thus reducing the likelihood of DOA

Mike

 

MikeBartley
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Re: Good reference
MikeBartley   7/24/2014 4:50:55 AM
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Thanks Roman

One other economic consideration is customer early engagement. If the early silicon is good enough for the client to use then they can often use it to clarify their requirements, start product development, etc

Mike

BillM210
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Risks and Rewards of early tapeout
BillM210   7/29/2014 10:08:44 AM
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Back in the late 1980's/early 1990's while at VLSI Technology, we always put a sample of spare gates into any ASIC design that we taped out.  Some customers had tight schedules to hit their primary selling time (Christmas sales).  To achieve the volume mfg that was required, it was critical to have safeguards just in case something was overlooked during their verification.  VLSI Tech (fab) would hold some wafers prior to metallization just in case some bugs were found.  Using this technique, our customer never missed their market and I would bet that this technique was used over 50% of the time (yes, either they missed all the requirements or the requirements had changed).  By integrating spare gates that had inputs tied to VSS, it allowed very fast changes with minimal mask charges and more importantly extremely fast re-spin of new silicon.  But this approach required careful and diligent hand editing of the physical database to alter metal/contact layers as well as a fab that was willing to split a lot.  To my recollection, if a re-spin was required, it only required one mask change.  Although designs requiring a metal re-spin were not considered a "first pass" success, it was very successful from the customer's perspective.

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