As Moore's Law reverses beyond 28nm, consider network-on-chip (NoC). While more and more content in SoC designs is coming from third-party IP providers, interconnect-fabric is one area that is still in transition.
As Moore's Law reverses and 20, 16, and 14 nanometer processes become more expensive, SoC cost reductions must come from design innovations within more mature processes and established methodologies.
The days are over when companies can expect to make a profit by introducing a so-so product at first but count on a second, higher-performing release manufactured using a smaller process.
Every design team knows the value of quality improvements in the following areas:
- Smaller die size
- Higher bandwidth
- Lower power
- Greater productivity
- Flexible quality of service
However, SoC design realities in the present era make it imperative to closely reevaluate mature semiconductor processes to realize greater efficiencies that yield lower costs, higher performance, and shorter time to market.
Since scaling to lower geometries won't yield the same economic or technological benefits that have fueled the semiconductor industry in the past, it's time to consider what else is possible to sustain business growth and technology innovation.
Simply put, it's time for the industry to pay more attention to optimizing the initial design of a chip, rather than betting on future process node shrinks to meet cost, performance, and power goals.
As Moore’s Law reverses, SoC companies should seek new ways to optimize the design process. The graphic illustrates the challenges of scaling in the semiconductor industry.
(Source: Mentor Graphics)
Better SoC design
Here are some quantifiable benefits of a better SoC design, and a better SoC design process.
Die size reductions of even 3 to 4 mm2 can save millions of dollars if the average price for silicon real estate is approximately 10 cents per square millimeter in a 28 nanometer process. For high-volume products, reductions of this size are possible and are currently providing fabless innovators meaningful economic advantage over competitors. Designers are also reducing wires and interconnect gates by as much as 50 percent.
Higher bandwidth connections within the chip can yield higher performance. On-chip links scaling beyond 1.6 GHz can improve performance within subsystems that run at 600 MHz and improve quality-of-service (QoS), particularly for multimedia data flows.
Lower interconnect power can reduce overall chip power consumption by as much as 0.7 milliwatts, significantly extending the time required between battery charges for mobile devices. While processor and GPU power consumption dwarfs that of the interconnect, they only operate for short periods of time. System-idle power, by way of the interconnect, is therefore the main determinant of system power consumption.
Productivity: Time is money in SoC design. Hardware and software teams consisting of 100 people cost about $24 million per year or $2 million per month. If one design process optimization can cut 30 to 35 days from delivery, that team can save more than $2 million in engineering costs, and get to market faster than the competition.
Time to market: If there were a way to cut two to three months off a development cycle, most design teams would be extremely interested in adopting it. Many fabless companies have already saved $4 million to $6 million in costs by accelerating time to market.
Design starts: Instead of producing one SoC every two years or every 16 months, it's now possible to deliver derivatives of one main design every five to eight months. Most companies struggle with interconnect during the late stages of the design cycle because of routing congestion and place-and-route issues. However, if those delays can be reduced or even eliminated, a fabless company can deliver more products to serve multiple markets.
How to quickly improve SoC design process
All of these improvements are occurring today, and teams that are benefiting from these profound market and performance advantages are leaving their old interconnect design methodologies behind. In their place they are adopting network-on-chip interconnect IP.
There are typically three choices to make in regard to the interconnect portion of SoC designs:
- Continue with internal efforts
- Interconnect IP comprising hierarchical buses and configurable crossbars
- Network-on-chip (NoC) technology
While more and more content in SoC designs is coming from third-party IP providers, interconnect-fabric IP is one area that is still in transition.
Internal efforts are inevitably falling by the wayside because IP content is rising, and teams assigned to the interconnect development task cannot keep up with the late-stage changes and rising complexity.
Interconnect IP comprising hierarchal buses and configurable crossbars are also struggling to keep pace with IP integration trends, where chips that used to have 15 IP cores at 40 nm, now have 40 or more IP blocks from multiple vendors at 28 nm.
Designers should evaluate interconnect technology that drives the highest quality of results. Lower product cost and hardware architecture flexibility should rate equally high on any priority list. NoC IP is best qualified for improving quality of results and productivity simultaneously.
If the overall SoC goal is to improve yield and quality and reduce costs, consider the advantages that NoC interconnect IP offers that competing solutions cannot:
- IP flexibility
- Tool automation
- Modeling output
- Layout-friendly modeling output
- Verification based on UVM methodology
- Automated test bench generation
- Heterogeneous protocol support
- FPGA emulation mapping
- Improved market responsiveness
Some of the most complex SoCs in the world include mobile application processors and digital baseband modems that have incorporate NoC technology as the SoC backbone interconnect fabric.
The improvements stated previously are all real-world numbers resulting from the work of Arteris customers. Optimizations resulting from the use of NoC interconnect technology helped these companies improve the performance and reduce the cost of their chips to offer clear market advantages.
Arteris has been delivering packet-based NoC interconnect IP solutions since 2006 and has built up considerable experience after more than 160 design starts, 85 tapeouts, and 50 production SoCs in electronic systems.
An effective NoC interconnect must have the complete set of features and capabilities described above to truly benefit SoC design in terms of quality, performance, and productivity.
The interconnect portion of any design should not be treated as a commodity: It is the backbone of the SoC, interfacing with all the IP functionality on the SoC.
When all of the benefits that an effective NoC interconnect bring to the SoC are added together, it is obvious that the performance and cost benefits can total tens to hundreds of millions of dollars depending on SoC complexity, SoC specification targets, number of projects, and production volume.
— K. Charles Janac is President and CEO of Arteris, where he is responsible for growing a strong global presence for the pioneer of NoC technology.