Are you working with DDR4? Interested in NVDIMMs? Designing at 100 Gbps? Wishing you knew more about data acquisition modes? Well, here are summaries of some systems design articles regarding memory that were published across the UBM Tech network this month.
Are you working with DDR4? Interested in NVDIMMs? Designing at 100 Gbps? Wishing you knew more about data acquisition modes? Well here are summaries of some systems design articles regarding memory that were published across the UBM Tech network this month.
"DDR4 memory interface: Solving PCB design challenges"
In this two-page design article, Agilent's Chang Fei Yee looks at four key challenges in designing the placement and routing of DDR4 SDRAM interface with multi-Gigabit transmission. The major challenges include the routing topology and termination scheme for nets with multiple receivers, routing technique to minimize crosstalk, method to mitigate the impedance discontinuity due to imperfect vias, and the method to maximize the timing margin of the data transmission. The study detailed in this article was performed by analyzing signal integrity using Mentor Graphics Hyperlynx with the import of IBIS models of Kintex UltraScale FPGA from Xilinx and DDR4 SDRAM from Micron. On EDN.
"Deliver at 100G: The impact of smart memory"
In this how-to article, MoSys' vice president of Technology Innovation and System Applications, Michael Miller outlines the challenges inherent in 100Gbps system design, and suggests the use of intelligent memories to offload functions to the memory subsystem. He recognizes that traditionally SRAM and RLDRAM have been used to build memory subsystems, but FPGAs and ASICs can be very challenged for pins at 100G. In addition, logic to perform error correcting code (ECC) adjustments, coherent increments, and token bucket updates impede traffic in crowded FPGA fabrics. In this article, Miller argues for the use of serial memory.
"In-memory database systems: NVDIMMs and data durability"
Designers often turn to in-memory database systems (IMDSs), which store records in main memory, eliminating sources of latency such as caching and file management that are hard-wired into DBMSs that store data persistently on hard disk or flash. As a result, IMDSs perform orders of magnitude faster than traditional “on-disk” DBMSs; their simpler design minimizes demand for CPU cycles, permitting the use of less powerful -- and less costly -- processors. Volatility, however, is sometimes a concern. In the event of power loss or system failure, main memory's contents are gone. This article offers solutions for IMDS volatility issues, in particular, the use of non-volatile dual in-line memory modules (NVDIMMs).
"Use the right data-acquisition mode"
In this article, Arthur Pini, measurement and analysis consultant and a popular contributor to EDN, teams up with Greg Tate and Oliver Rovini to take a closer look at modular digitizers. This design piece provides an overview of the different ways to trigger and capture signals.