Who needs to eat lunch when you can use the time to build and study a digital clocking circuit?
Did you know that you can use a D-type flip-flop to position a clock edge to sample a jittery digital data stream very close to the midpoint of a bit's average unit interval? You can use the rising edges of the data to clock the Dflop and sample the state of the recovered clock to seek its falling edge. Then the rising clock edge (assuming 50% duty cycle) naturally falls almost exactly at the eye center -- right where we want it.
The unusual aspect of this circuit is that the Dflop seeks its own point of metastability, but unlike with most other digital applications, the use of follow-on analog integration lets us get away with this. Yesterday, I remembered that I had a 3.088 MHz voltage controlled crystal oscillator (VCXO) in the junk box, and for a current project, I happened to have a 1.544 MHz fixed-frequency crystal oscillator. With a 74F74 Dflop also on hand, I had all the ingredients to breadboard this circuit and have a closer look at metastability. So I assembled the circuit on a plastic breadboard and started probing. The results were a bit surprising. Here is the breadboarded circuit.
A breadboarded PLL that locks the 3.088 MHz VCXO signal to a data reference at 1.544 MHz.
I don't have a 3.088 MHz random data source, and I built this circuit on my lunch hour. Thus, I didn't have the time to build the data source. Instead, I used the fixed-frequency 1.544 MHz crystal oscillator, which generates an alternating one-zero data pattern at 3.088 Mbit/s. It produces some clean edges, so I couldn't simulate jitter or do any fancy measurements such as jitter transfer at specific jitter frequencies (maybe next time, if I get hold of another VCXO that can be frequency modulated).
The rising edges of the 1.544 MHz data sample the 3.088 MHz VCXO output and servo the VCXO frequency/phase, so they are time coincident with the falling edges of the 3.088 MHz signal. This is the point of maximum metastability.
The loop filter is a 1 kΩ trimpot and 1 µF capacitor. (I should have used a smaller cap to gather results faster.) The trimpot lets me adjust the damping factor by varying the ratios between the upper portion (R1) and the lower portion (R2). Surprisingly, once away from the unstable region (R2 too low), the jitter on the recovered 3.088 MHz clock did not change a lot at various damping factors. I would have liked to measure some jitter transfer, but I had neither the time nor the equipment. Maybe you can try this at home.
The Dflop on the far right of the schematic above was not included on the breadboard; it's shown simply to illustrate how a real system would use the phase-locked 3.088 MHz to sample the incoming data at the eye center and reduce its jitter using the averaging effect of the loop filter. For the purpose of this exercise, I just wanted to create the conditions for metastable events, so we can study them.
The yellow trace is the active rising sampling edge of the 1.544 MHz data at the Dflop clock pin.
In the image above, the yellow trace is the active rising sampling edge of the 1.544 MHz data at the Dflop clock pin. The blue trace is the phase-locked falling edge of the 3.088 MHz from the VCXO at the Dflop data pin. The scope is set for infinite persistence to show accumulated timing jitter. Unfortunately, the scope's FFT function lacks sufficient resolution to show phase sidebands. The waveforms look pretty nasty, being on a plastic breadboard with four-inch scope probe ground leads. Someday, I might try this again on a real copper-clad breadboard. That should improve the signal fidelity.
Now let's hunt for some metastable events at the Dflop Q output pin resulting from the above timing violations.
The oscilloscope's infinite persistence has captured some
This figure shows signals triggered on the rising 1.544 MHz data edge for several minutes. The infinite persistence has captured some metastable events. It looks like the few falling edges, once started, always continue downward. However, the many rising edges change their minds, falling back to a low if they lack the momentum to make it all the way up the hill.
Let's look closer at the Dflop's rising-edge metastability by triggering on the events themselves. The oscilloscope screen below shows that triggering on the rising edge of the Dflop output at a high level weeds out all the minor events. This helps us see the larger excursions that did not quite make it up the hill.
Triggering on the rising edge of the Dflop output at a high level weeds out all the minor events.
Come back Tuesday, Aug. 26, for the conclusion.