Yesterday in Breadboard for Lunch, we saw that you can use a D flip-flop as a VCXO and place a rising edge in the center of the average bit interval. And now, the conclusion. But first, here's the circuit schematic again (Figure 1).
A breadboarded PLL that locks the 3.088 MHz VCXO signal to a "data" reference at 1.544 MHz.
In Figure 2 below, you can see triggering on the falling edge of the Dflop output won't capture any falling edges that change their minds and rise again. Some rising edge ghosts were captured because of their subsequent falling edges. What is also very different is that while the falling edges always keep on falling, the increased time smearing of the yellow 1.544 MHz clock trace indicates that the falling edges are prone to varied delays in their response. In other words, they take extra time to make the stay or fall decision, but once started falling there's no turning back. So, why is there a difference between rising and falling metastable reactions?
Triggering on the falling edge of the Dflop output won't capture any falling edges that change and rise again.
Now let's look at the long-term variations at the Dflop output.
The ugly response in Figure 3 at the Dflop output keeps the loop locked. This is the point of the trimpot adjustment that seemed to result in minimum jitter. Reducing the damping factor resulted in the noisy edges merging together. There were, however, periods of steady logic high with closed periods of toggling with no steady periods of logic low. But, the jitter on the 3.088 MHz VCXO didn't vary by much. I also can't explain why the periodic alternation between high and low and the duty cycle offset. I would have thought a 50 percent random noise waveform here, but maybe it has something to do with the difference in metastable response of the rising versus falling edges. Maybe it's the fact that TTL drive is a voltage source, not a current source. Maybe it's caused by being on a plastic breadboard. I did observe that adding a second probe (15 pF) to the Dflop output changed the pattern slightly.
The Dflop output keeps the loop locked.
Finally, I tried forcing the loop into its unstable region by setting the trimpot for R2=0 (no phase margin). The jitter on the 3.088 MHz clock jumped up to about 10 ns (Figure 4), but the loop remained somewhat locked. The Dflop output excursions remained at the extremes for much longer (about 10 times) and appear to abruptly and decisively change logic states.
Forcing the loop into its unstable region by setting the trimpot for R2=0 (no phase margin) caused jitter on the 3.088 MHz clock to jump up to about 10 ns.
Zooming in to 1,000x (Figure 5), the sweep speed reveals that as the signals drift out of the timing violation region, the metastable action builds up to a final amplitude and the signal "Made it to the top of the hill!"
The metastable condition's amplitude eventually rises high enough for the digital logic signal to change state.
This little lunch-hour safari into the metastable jungle has led to more questions than it answers. I wonder how other logic families would respond to the same induced timing violations? Are you up to experimenting with this and/or doing some theoretical analysis?