Emerging capital market high-frequency trading (HFT) is bringing strong FPGA use cases in networking, messaging, and financial computing acceleration.
Pre-trade risk management acceleration
HFT extensively draws on statistical laws of large numbers to promise the investor fair but steady revenue with little or no risk of loss. Risk management (RM), being central to any financial environment, is hence an essential component as it runs in the background, guides the execution engine, and drives stop-loss signals as necessary. RM algorithms may be very complex, use much of known DSP functions/blocks, and require the ability to be reconfigured at the user's discretion.
Brokers are gaining attention. Celoxica, which traditionally offered a comprehensive suite of multi-venue feed handler appliances, recently released a multiple-asset market access gateway, allowing configurable real-time RM for numerous HFT clients within a few microseconds. On another hand, GateLab's FPGA risk gateway PCI-e card features multiple FIX market connectivity, normalizes market access, controls operational risks, and executes orders accordingly in less than 5 µs.
Order execution management acceleration
HFT servers execute long-term strategies and portfolio management software components that oversee the profitability of the overall operations. Under RM control, execution management maintains an order book that keeps acquired market data records relevant to the trader's portfolio and runs an execution algorithm that makes buy and sell orders (ensuring their distribution is hard to associate with).
NovaSparks offers a unique pure FPGA order book builder alongside its FIX feed handler. This stores order records in a venue-agnostic format, thereby allowing the development of execution algorithms targeting multiple venues without overlapping formats. The build process overhead is a deterministic 500 ns. The previously cited Enyx market data access appliance also performs an order book building function.
Market data processing acceleration (ticker plants)
Ticker plants are proprietary hardware "big data" aggregators, processors, and distributors. They receive fresh market data at the exchange (matching engine input and output) or through the financial network. Many cumulative statistical indicators, referred to as level-2 market data, are computed on-the-fly at the ticker plant.
Exegy is the classical ticker plant vendor, but there is a recent product release by Celoxica.
Real-time performance management
AdvancedIO believes that it is critical to continuously improve trading platform performance through precise latency monitoring, especially for distributed systems. The PTP (Precision Time Protocol) specified in IEEE 1588-2008 is a de facto industry standard that enables sub-microsecond clock synchronization. A PCI-e card -- in conjunction with an FPGA PTP offload -- timestamps events in real-time and feeds them to an analytic engine for assessing and reporting on performance. There are several leading companies involved in PTP FPGA hardware with a broader perspective than just for HFT.
The vendors and products cited above are by no means exclusive; rather, they reflect distinct developments in each of their respective areas. There are more than a dozen innovators offering specific products of direct benefit to the HFT business. Having said this, it is worth noting that Altera's Stratix V FPGAs are a leading common implementation choice.
FPGA deployment in HFT is rising in magnitude and widening in functional coverage. Handling market data is of highest merit and demands the most streamlined implementations. Brokers will eventually benefit most since they act on behalf of many users, running different strategies and dealing different securities over multiple venues. Performance monitoring is gaining attention thanks to its being universal to all platforms and critical to tuning software and hardware components' performance. As the latencies of software components begin to dominate end-to-end, one would expect parameterized realizations of proprietary risk, execution, and matching algorithms, as well as overall algorithm development hardware platforms, limiting the CPU motherboard in HFT environments to perform only system management functions.