The latest radio processing unit (RPU) architecture from Imagination Technologies is clearly demonstrating the impact of the Internet of Things on the design of IP and system on chip (SoC) devices.
While the software defined radio (SDR), the approach that Imagination's Ensigma division pioneered, has been adopted across digital radio and consumer WiFi chips, the flexibility of SDR comes at too high a cost in terms of power and expense.
As a result Imagination has moved to a more traditional, but configurable, approach for its latest Whisper RPU. Instead of a fully flexible RPU design like its Explorer core, Imagination has made Whisper deliberately optimized for the lower bit-rate standards. It can still handle a range of protocols, from 802.11n WiFi to all forms of Bluetooth to 802.15.4 Zigbee and 6LoPAN, but only configured at the design stage for the specific protocol or set of protocols.
This hardwired approach is the way to reduce cost and more importantly power, says Imagination, using its SDR experience to reduce the power consumption throughout the signal chain from the processor to the transmitter.
Imagination has also taken the opportunity to more tightly integrate its latest MIPS Warrior processor cores with the RPU to handle some of the MAC functions such as packet processing, encryption and queue management that can take up extra silicon. Having the MIPS tightly coupled to the multiple MACs that can be used for different protocols also allows for more efficient arbitration between channels, potentially reducing the average transmit power as there is less interference to overcome.
The MIPS core can also be used as a 'mini-host' to manage other peripherals and leave more cycles for the main applications processor in the IoT or wearable node, while virtualization support can also provide security and trusted root implementations that are increasingly important in IoT.
The change is to use separate configurable blocks for the modem, bit processing and control so that each block can be mapped to the requirements of a particular protocol with lower data rates. This allows the modem to be optimized with more space and power efficient designs, fro example replacing a 64QAM modulation with 16QAM which is sufficient for lower bit rates such as 802.11b or the coming 802.11ah sub-GHz protocol. As a result the architecture will scale up to 802.11n at 72 Mbit/s and notionally a 2x2 MIMO version of 802.11ac, but will typically be optimized for data rates topping out at 24 Mbit/s to 36M bit/s, says Richard Edgar, director of communications technology marketing. Once you reduce the bit width of the modem you can reduce the width in the bit processor below 10bits, again saving space and power.
Imagination points to the implementation of WiFi as a prime example. What Whisper allows is a reduction of 50% in size and almost 50% in power moving from the full 802.11ac WiFi to a more optimized version, says Chakra Parvathaneni, Senior Director of Business Development for Ensigma. As you would expect with a modern design, there is also lots of clock gating and fine grained power management to allow individual blocks to be switched off when not in use to reduce the overall power using the PowerGearing technology introduced in the PowerVR graphics cores launched in January.
Imagination is keen to point out that Whisper still provides multi-standard support in a single architecture, enabling its chip customers to bring standards such as Wi-Fi, Bluetooth Classic, Bluetooth Smart, NFC, GNSS and other existing or emerging low-power connectivity technologies onto their SoCs.
However Bluetooth for example wouldn't use this type of optimization, leaving the power consumption at 3mA to 4mA that is comparable to other device sin the market, says Edgar, so it is the combination of low power WiFi with other protocols that is the key to the Whisper proposition.
Imagination is also keen to point out that this is the architecture announcement, not the implementation of the protocol stacks or the partitioning between the hardware and software in an IP core that has been simulated. Indeed, Imagination refers to this as "hardware assisted," indicating that substantial protocol processing will be handled in the MIPS Warrior core. How the different blocks will be combined for different combinations of protocols will determine which MIPS processors are used, but this will also be determined by the customer requirements.
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