Integrated circuit designers have always had a challenging job, but in the last few years, the complexity of IC design and verification has risen significantly.
Electronic design automation (EDA) tools have responded by adding and expanding functionality, but, not surprisingly, that additional performance increases the complexity of using the tools. Design teams trying to understand and implement new design requirements want to spend as little time as possible simply figuring out how to perform essential tasks.
If you are a chip designer or a CAD person trying to find answers about how to use EDA tools to solve a design problem, then time is of the essence, especially if your questions are pertinent to your own design flow. Time to signoff is your critical gating factor, and every moment of time you spend not directly engaged in design and verification is a moment of opportunity lost.
Years ago, your only options would have been to plow through the user manual, or to contact the support staff of your EDA vendor.
Even the advent of online documentation only nominally improved the time required to find the information you were looking for. What was needed was some way that let users walk through the specific process they needed, such as how to extract a net from a GDSII file or convert LEF macros to GDS or OASIS files quickly and efficiently, allowing them to get back to work with the exact knowledge they needed, with minimal interruption to the design flow process.
Enter the video. Videos have become nearly ubiquitous in today's interconnected, real-time, wireless world. People post and watch videos with their laptops, their video cameras, and their cellphones. And videos can be tailored to provide as little, or as much, information as needed.
Why not put that technology to use in the IC design and verification support space?
So, we did.
About a year ago, we began isolating specific activities that seemed to generate a lot of support requests, and began producing short, targeted videos that demonstrated the proper execution of a given task. Let me show you an example.
The process of taping out a chip is a continuous collaboration between the design house and the foundry that includes a constant exchange of information between them. For example, the following types of data exchanges are routine during the physical verification flow:
- The design house sends selected design rule checking (DRC) violations to the foundry for waiver approval.
- The foundry reviews and approves waived error results from intellectual property providers.
- A foundry suggests changes to design layouts that a design house can implement to improve yield.
- The foundry and design house both finalize and freeze the design database and archive the verification data.
In addition, groups within the same company might also need to exchange detailed data to make important decisions about their designs.
Manual report preparation and communication of this information has always been a significant time sink in the physical verification process, and the quality of the information provided is often dependent on the expertise and experience of the individual who prepares it.
In most of these reports, the information transferred includes a visual "snapshot" of a specified layout area (with or without error markers), and a description of the pertinent details.
Designers use snapshot tools to create the layout snapshot, and word processing or presentation tools to generate the accompanying explanation. Some companies may use in-house scripts or programs to automatically generate all or some of the report information, but even these programs still require additional time and resources to create and maintain them.
As you would expect, the process is cumbersome, and can take a significant amount of time both in data preparation and transfer. Security is also a constant concern, as emails can be misdirected, intercepted, or inadvertently deleted.
Recognizing this issue was a major opportunity to help our users, we developed an automated DRC HTML reporting capability that improves the efficiency and accuracy of the DRC debugging process while eliminating the need for time-consuming document preparation.
However, implementing the actual functionality revealed that users needed a little help the first few times through. So we began creating "How-To" videos to demonstrate different parts of the process.