A formal verification signoff project on a design-sized block usually takes 3-6 months. A good plan can make the difference between success and failure.
Over the last couple of months, my family took an extensive trip across China, covering as far as Tibet in the southwest, the Silk Road in the northwest, and Heilongjiang Province in the northeast. We saw many beautiful sights and learned about China's ancient history and Tibetan Buddhism.
Though the trip was only five weeks long, it took me months to plan. First, I researched what we wanted to see and do. I searched the web and approached friends and family, who offered their opinions. At the end of the process, I had a few places in mind.
Next, I needed to decide if all I wanted us to see would fit within the time we had available. After all, it would take months to see all the many beautiful sights in China. Money was also a consideration. I had to find the balance between desire and reality to decide what could be done within our time and budget.
Finally, it was time to put the actual plan together. This included buying airline tickets, booking hotels, and deciding what to do each day and how to get there.
By the time we began the trip, I had a thick stack of paper containing all the information. The trip largely went as planned, except for canceling one day's itinerary due to high altitude sickness in Tibet. (The highest point we reached was 5,013 meters.) Overall, it was a memorable trip, and this has to be credited to my diligent planning beforehand.
Looking back, what I did for our trip was not that different from the formal test planning companies should undertake before embarking on a formal verification project. Planning is crucial to formal verification success.
A three-step process ensures success and echoes the steps I took for my family's travel.
Decide on what to verify with formal verification. In this step, the verification engineer must decide what the goals are for applying formal verification. Is it finding bugs, improving simulation coverage, reducing project cycle, learning formal, or -- most daring -- achieving formal signoff? These goals dictate what kind of formal verification to apply.
Formal verification is a powerful technology, but it is not suitable for all design types. Control and data transport types of design blocks are better candidates than data transform designs, for example. Coming up with a target list of suitable blocks to perform formal verification on is important.
During this step, the engineer should look at the availability of human resources and formal verification expertise in the team. This impacts what can and cannot be done.
Determine what can be achieved within the resource, budget, and scheduling constraints. Finding the balance point between desire and reality in the context of verification is more complex than the challenge I had in planning our exploration of China, but the essence is the same -- finding the point that gives the best (verification) return on investment.
This step requires careful consideration of many factors, such as design interfaces, register transfer level (RTL) metrics –– e.g., register counts, RTL lines of code, the number of inputs and outputs, parameter variations –– and critical design functionalities. All need to be considered for a good understanding of the proposed design under test to gauge how much effort it will take to formally verify it and whether appropriate resources are available.
At the end of this step, there should be a mapping between each candidate design to one or more formal testbenches, along with a determination of who is responsible for developing which testbench. It is common that only a subset of the target blocks is chosen at the end of this process.
Pull everything together and create the actual implementation plan stating the who, when, and what. An actual English list of checkers and constraints should be captured in this step. Formal complexity should be explored to plan for a solution. Exact metrics to measure success, such as coverage metrics, need to be established. This is the blueprint for the actual execution of building a formal testbench and performing actual formal verification to achieve the stated goals.
Of course, I could have taken a weeklong trip without much planning. In the case of a five-week trip, however, I am glad I did careful planning, so we didn't get stuck somewhere in China. A formal verification signoff project on a design-sized block usually takes 3-6 months. Here at Oski Technology, we have completed many formal verification projects, and we can confidently affirm that planning is required to succeed.
-- Jin Zhang is senior director of marketing and general manager for Asia Pacific at Oski Technology. She has more than 15 years of experience working in EDA, driving the effort of bringing new products and services to market. At Oski Technology, she is responsible for its overall marketing strategy as well as business development in Asia Pacific. Previously, she was general manager at EVE-China and director of technical marketing at Real Intent. She has also worked at Cadence Design Systems and Lattice Semiconductor Corp. She holds a Ph.D. in logic synthesis and verification and a master of science degree in international management with a focus on Asia Pacific, both from Portland State University.