STT-MRAM can replace low-density DRAM and SRAM, especially for mobile and storage devices. But what is it and how does it differ from MRAM?
Memory is one of the most important defining components used in every computer system, storage solution, and mobile device in existence today. Performance, scalability, reliability, and the raw cost of memory are major criteria in determining the economic success or failure of each system product brought to market.
Nearly all of today’s products use one or a combination of charge-based, volatile memories, DRAM and SRAM, and non-volatile memories NOR and NAND flash. These existing memories have significant advantages that led to market dominance over the last 30 years. They also come with drawbacks that cloud their future, since systems consistently need to be faster, smaller, more reliable, and less expensive to compete effectively over the next five to ten years.
There are new disruptive technology challengers coming into the market, specifically non-volatile memories (NVM) such as resistive RAM (RRAM) and phase-change RAM (PCRAM) that promise high performance, low power consumption, and unlimited endurance. Magnetic RAM (MRAM) is one of these emerging technologies.
Note that MRAM is not new -- it was first presented at industry conferences more than 25 years ago. It created a lot of excitement back then since it was so different from the charge-based memories. There are now a few different types of MRAM being deployed today, including field-switching and heat-assist MRAM. All have distinguishing characteristics making the technology useful for different kinds of niche applications.
Spin-Transfer Torque (STT) MRAM, however, is well suited for many mainstream applications, particularly as a storage technology, since it delivers the high performance of DRAM and SRAM, has the low power and low cost of flash memory, scales well below 10nm, and leverages existing CMOS manufacturing techniques and processes. Since it is non-volatile, STT-MRAM will also retain its data indefinitely when the power is lost or completely turned off.
Unlike a much-anticipated newcomer RRAM, the basic physics behind MRAM as a storage device is well understood. With MRAM, a memory cell is comprised of a magnetic tunnel junction (MTJ), which has been widely used as read head for hard-disk drives for many years. Early MRAM devices utilized in-plane MTJ (iMTJ) where the magnetic moments (a vector having a magnitude and direction) stay parallel to the substrate silicon surface (see Figure 1).
In-line MTJ diagram.
There is now another, more-optimized version of MTJ, called perpendicular MTJ (pMTJ), where the magnetic moments are perpendicular to the silicon substrate surface (see Figure 2).
Perpendicular MTJ diagram.
While the iMTJ-based STT-MRAM does not scale well below 90nm nodes and is not cost competitive on 200mm wafers, the pMTJ-based STT-MRAM scales extremely well, down to below 10nm. It is expected to be cost-competitive with other memory technologies, such as DRAM. This scalability enables STT-MRAM to become the viable alternative for DRAM and flash in low- and medium-density applications over the next few years.
In a typical STT-MRAM integration process, the MTJ resides between two metal layers requiring two additional masks. While the early processing relied on the tools that were designed for the hard disk drive (HDD) industry, in recent years the big equipment tools vendors in semiconductor manufacturing have been developing the key deposition and etching tools needed for 300mm wafer processing. Thus there is now an ecosystem in place for manufacturing STT-MRAM in high volume on 300mm wafers at less than 40nm.
A key attribute of STT-MRAM is it uses the standard CMOS transistor, and the MTJ processing is handled in the back-end of the line (BEOL). This makes the manufacturing process seamless and therefore ideal for high volume, low-cost production of both standalone discrete as well as embedded applications.
As a discrete memory device, STT-MRAM is being used as a replacement for SRAM, DRAM, and NOR-flash due to its higher speed, lower latency, scalability, and unlimited endurance. STT-MRAM does not require a power-refresh like DRAM, and the read process is not destructive. This situation provides a significant power advantage, as well as lower latency at the system level.
In many of today’s SOCs, CPUs, and GPUs, between 50% and 80% of the die-area is consumed by memory. This embedded memory tends to be mostly SRAM using four or six transistors. In comparison, STT-MRAM uses one transistor. Recent CPUs have also shown the incorporation of e-DRAM to save die-size, in spite of its being a very difficult process. STT-MRAM, with ease of integration due to standard CMOS, is ideally suited for such applications. It provides a significant die-size reduction while providing high-speed NVM close to the logic. This is expected to provide a lower cost, a faster boot time, and a number of new functionalities, especially for mobile and storage devices.
Enterprise storage is the major application fit for pMTJ-based STT-MRAM. Storage arrays and datacenters are undergoing a dramatic change from old legacy HDD-based systems to all-silicon (solid state drive, SSD) flash-based systems. At the same time, the software-defined datacenters, networks, and storage, in combination with virtualization, will continue to transform the whole data-storage space in the coming years.
For more on STT-MRAM, see Avalanche Technology’s website.