One of the significant advantages of MIPI Alliance standards is the separation of the physical or PHY layer from the protocol layer. This approach contrasts with USB, PCI Express, or SATA, where these layers are specific to a particular protocol, and provides much needed-flexibility to deal with the many sensors and peripheral devices found in a typical mobile device while preserving the core PHY objectives of power conservation with headroom for higher data throughput.
To date, MIPI has published 30 different specifications but it only has two PHY specifications: D-PHY and M-PHY. All the display, camera, RF, storage interfaces, etc. layer on top of just these two PHYs. MIPI sees M-PHY as the high-performance PHY with speeds up to 5.8 Gbps while D-PHY is more for cameras and displays and lower-speed applications.
With low-power operation, high-performance, and flexible protocol support, it would appear that the MIPI canvas is a done deal. But, as with all things in technology, especially mobile technology, it's never that simple. Now MIPI is in the process of releasing a third PHY standard called C-PHY.
Does the world need another MIPI PHY? Perhaps. As the use of the letter "C" implies, C-PHY is designed for use with cameras -- a key point of differentiation for many mobile devices. It will offer improved throughput performance compared to D-PHY while maintaining backward compatibility with MIPI CSI-2 (Camera Serial Interface). C-PHY also picks up low power mode from the D-PHY spec.
Unlike M-PHY, which needs to act as a general purpose data bus with traffic flowing freely to multiple interfaces, the role of a camera interface is much different. Its role is to move pixels from the camera to memory as quickly and efficiently as possible. As such, it shouldn't come as a surprise that C-PHY takes an interesting departure from the other MIPI PHYs, one that is likely to present new test and measurement challenges.
Both D-PHY and M-PHY use standard differential pairs for data transmission. In the case of D-PHY, one data lane consists of two differential pins and two pins of differential clock; a four-lane interface would consist of four differential pairs (eight pins) plus one differential clock pair for a total of 10 signal pins. It uses a conventional clock-forwarding technology.
In contrast, C-PHY uses a 3-pin architecture and an embedded clock. Each of the pin trios represents one lane with up to three lanes supported for a total of 9 pins. It also uses a new encoding scheme to increase the number of bits transmitted to approximately 2.28 bits per symbol. The projected data rate is 2.5 Gsymbols/s for an effective data rate of about 5.7 Gbits/s.
A further C-PHY nuance is that the signal is transmitted single-ended, but received as a differential signal. Clock is recovered from the earliest edge of the symbol transition. A delay circuit with negative hold times is used to sample data, an approach that is potentially more resistant to noise and jitter.
While C-PHY is still being finalized, it's never too early to start thinking about compliance testing challenges, of which there are a few. Questions will revolve around jitter and eye mask definitions, clock recovery techniques, and determining acceptable BER levels.
Introspect, which recently announced an early C-PHY analyzer product, commented: "C-PHY is an emerging physical layer standard that allows for significant bandwidth improvements on constrained transmission channels such as those found inside mobile terminals. it’s important to be able to confidently assure transmitter device performance and interoperability with a proven, third-party supported reference standard that incorporates all necessary C-PHY technologies such as dynamic termination and multi-wire clock recovery." As with the other MIPI PHY standards that have received broad industry support, it's safe to assume we'll be seeing many more C-PHY related announcements in the coming months.
In my next post, we will look at compliance testing requirements for M-PHY Gear 3.