Breaking News
Blog

Analog Bits to Design Mixed-Signal IPs for China

Phase II of IP licensing wave in China
NO RATINGS
View Comments: Threaded | Newest First | Oldest First
junko.yoshida
User Rank
Blogger
Phase II of IP licensing wave in China
junko.yoshida   8/19/2014 11:22:36 AM
NO RATINGS
We've covered extensively how those global IPs from ARM, Imagination and Ceva have helped China fabless.

Time to pay attention to what's going on with the mixed-signal IP world. The Analog Bits' executive see that Chinese fabless chip companies are no longer satisfied by using standard IPs that they can get almost free from TSMC or EDA companies.

Susan Rambo
User Rank
Blogger
Re: Phase II of IP licensing wave in China
Susan Rambo   8/20/2014 4:39:40 PM
NO RATINGS
You wrote "for a majority of Chinese fablesses, Analog Bits' IPs will come as "design kits." The IPs will be physically integrated into a chip in a clean room at TSMC, explained Tirupattur. He regards this process as a firewall to protect their IPs."

Do you have any more information on this? I don't understand how a design kit will help protect IP.

Mahesh.Tirupattur
User Rank
Rookie
Re: Phase II of IP licensing wave in China
Mahesh.Tirupattur   8/20/2014 5:42:04 PM
NO RATINGS
Dear Susan,

Mahesh here from Analog Bits 

Design kits typically come in 2 flavors

Front-end design kit which would include Verilog, .libs and foot print views such as LEF 

Back-end design kit which would include Front-end views and GDSII and Spice netlist (which is indeed the source of the hard IP). 

For most companies we will release only Front-end design kits whereby the customer can complete the entire design without the GDSII and when they are ready for tape-out they would merge the GDSII at the fab. We have done this successfully in the past and the fabs also support this program. 

The advantege of this approcah is we can protect the IP for the specific fab and we can help the customer tape-out quicker as well.

 

Please do not hesitate to ask any further questions or contact me directly at Analog Bits

 

regards

-mahesh

Susan Rambo
User Rank
Blogger
Re: Phase II of IP licensing wave in China
Susan Rambo   8/20/2014 5:51:44 PM
NO RATINGS
Thanks, Mahesh for the speedy response, and thanks kmonsen for the added explaination. 

kmonsen
User Rank
Rookie
Re: Phase II of IP licensing wave in China
kmonsen   8/20/2014 5:48:10 PM
NO RATINGS
That means they won't release their LVS netlists or GDS2 to the customer -- only Verilog behavioral model, Liberty timing models, that type of thing.  Nothing revealing the circuit design.

August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
5 comments
Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll
Radio
LATEST ARCHIVED BROADCAST
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.