A stable voltage supply is perhaps the most basic of all requirements in power system design. As the latest microprocessors, DSPs, and FPGAs require decreasingly low voltages -- from 3.3 V down to as low as 1 V with tolerances as small as ±30 mV -- this can place severe demands upon the power system.
Most types of circuits demand dynamic input current for short periods of time, and the power system is designed to handle fast dynamic current by means of decoupling capacitors, while the power supply handles low frequency and longer duration dynamic demands. The power supply control loop, the distribution impedance, and the decoupling capacitors determine how the dynamic current is shared between the decoupling capacitance and the power supply.
Certainly, the employment of intelligent digital power can make a massive contribution in handling load changes and also enabling energy savings. However, the introduction of digital technology in point-of-load (POL) power converters has meant that some will struggle when designing appropriate control loop compensation. Clearly, digital power control is not some form of magic that twists the laws of physics -- the apple falling from the tree still moves in an entirely predictable direction -- but what digital control can do is to improve and optimize dynamic response performance.
Digital protocol does not have to take any tolerance problems into account, which is the case for capacitive and resistive networks used in analog control loops. A common approach is the use of traditional analog tools to determine a solution, which is then transformed into the digital z-domain. And, of course, this can be time consuming and often generates a non-optimal solution. What would be most useful is a tool that can design, simulate, analyze, and configure a POL regulator directly in the z-domain within minutes.
One totally free tool that is available for this purpose is the Ericsson DC/DC Digital Power Designer software. Robust design algorithms are implemented in the software that can automatically generate optimized solutions; however, design and analysis tools are also available to advanced users.
The mathematical model of the power converter is based on the POL of interest and is generated using graph theory and Hamiltonian modeling. The model allows direct design and analysis of digital compensation in the z-domain, simplifying the design process by omitting tedious transformations between the s- and z-domains.
It therefore becomes very possible for the power system designer to fine-tune a POL regulator's control loop for the particular application and significantly improve and optimize the dynamic response performance and/or reduce the required decoupling capacitance. Overall, this means fewer output decoupling capacitors can be used to ensure a given voltage tolerance, which obviously translates into lower component cost and correspondingly delivers an increased system packaging density and reduced time-to-market.
For more information on loop compensation, there is a technical paper available from Ericsson, titled "Loop Compensation and Decoupling Design With 'The Loop Compensator'."