It is fitting that the IEEE S3S Conference 2014 would be the forum at which a key decisive breakthrough for monolithic 3D IC technology will be presented.
The forthcoming IEEE S3S Conference 2014 on October 6 through October 9 will be the first such event to focus on the emergence of monolithic 3D technology. In fact, it is fitting that this would be the forum at which a key decisive breakthrough for monolithic 3D IC ("M3DI") technology will be presented. This game-changing breakthrough is the first-ever monolithic 3D flow that allows a fab to build a monolithic 3D integrated device while using its existing transistor process flow, without the need to develop and qualify new transistors and a new transistor formation flow.
Recent columns -- such as Established Nodes Getting New Attention and Moore's Lag Shifts Paradigm of Semi Industry -- have articulated the building up of interest in SOI, Sub-threshold, and 3D IC technologies. The IEEE S3S is the venue to become updated on all of these technologies, including M3DI, which is the newest technology to be integrated into the conference. The 3D part of S3S 2014 will have a full day of tutorial presentations by leading researchers in this space, and will conclude with a session dedicated to discussing the most recent breakthroughs in the field.
The M3DI short course will cover alternative process flows that enable M3DI, discuss the challenges and solutions with regard to the removal of heat from monolithic 3D stacks, and describe the full range of powerful advantages provided by M3DI. Subsequently, Professor Sung Kyu Lim of Georgia Tech will cover EDA for M3DI. This will be followed by broad coverage of M3DI for memory applications by two leading experts in the field -- Akihiro Nitayama of Toshiba/Tokohu University and Deepak Sekar of Rambus.
M3DI provides unparalleled heterogeneous integration options, which will be covered by Professor Eugene Fitzgerald of MIT and SMART Lee Institute of Singapore describing the integration of silicon with other crystals for electro-optic device integration. The short course will conclude with Professor Philip Wong of Stanford, who leads research efforts to integrate silicon with carbon nanotubes and advanced 2D transistors layered with memory such as STT-MRAM and RRAM.
In the special invited "3D Hot Topics" session, we expect to get a full spectrum of the latest progress in the field. Particularly worth noting is the recent progress in the work performed by CEA Leti, supported by Qualcomm with the involvement of ST Micro and IBM. This work shows both a practical path to monolithic 3D ICs and a cost analysis of the various monolithic 3D advantages. The following chart illustrates the reasons for the high interest in this technology.
And then there is the great dessert to this 3D feast. On Thursday afternoon, in the "3D New Developments" session, the game-changing technology I referred to earlier will be presented. Leveraging breakthrough progress in wafer bonding technology, for the first time ever we will be presenting a monolithic 3D flow using an existing fab transistor process. Any fab could utilize this breakthrough to provide far better products with minimum capital and R&D investment. This game-changing flow removes the historical differentiation between sequential and parallel 3D, and should significantly reduce the time for monolithic 3D adoption throughout the entire semiconductor industry.
For the attendees' postprandial enjoyment in the "Late News" session, CEA Leti will present a fully constructed M3DI SOI device, and IBM will present its Multi Stacked Memory wafer technology.
More information is available on the conference site at S3SConference.org.