REGISTER | LOGIN
Breaking News
Blog

Manufacturing RRAM: Challenges & Opportunities

NO RATINGS
View Comments: Newest First | Oldest First | Threaded View
resistion
User Rank
Author
Efficiency
resistion   10/15/2014 12:18:54 PM
NO RATINGS
I think any 3D NVM technology (NAND or RRAM) has to answer the area efficiency problem. Sure, the vertical stacking prevents the area of the array from growing, but the circuitry to handle more bits at a time is likely increasing the chip footprint. In fact, for Samsung's 2nd generation 3D NAND, it looks like the area efficiency is definitely way below 90%, which threatens the ability to increase capacity. And putting the circuitry under the array definitely takes more steps and layers.

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed