DesignCon promises a smorgasbord of sessions on high-speed interconnect engineering at the chip and board levels, including a look at issues on the bleeding edge of 56 Gbits/second and beyond.
Many of the world’s top engineers in high-speed chip and board interconnects will gather next month at DesignCon. Here’s my take on the annual event’s top sessions.
I think DesignCon is all about pushing the envelope. Three sessions standout for me as clearly focused on pedal-to-the-metal engineering.
These days 56 Gbit/second links are at the limits of what’s possible for serial links. So I expect to take a seat in a Rambus session on serial interconnects at 56 Gbits/s and beyond.
Another evergreen topic is the transition from copper to optical interconnects. Silicon photonics has been getting a lot of attention for being in the vanguard of that shift given developments and acquisitions at companies including Cisco, IBM, Intel, and Mellanox. A session on the topic promises to be a frank exploration of the reality underneath the hype.
The final of my three top sessions is also about the copper/optical transition. A panel on optical backplanes pulls together an impressive group of system and component experts who I expect will give a realistic picture of what’s to come in the next year.
Not everyone lives at the bleeding edge. Just one step back from it, many engineers are trying to drive interconnects to 32 Gbit/s and beyond. That’s the topic of another one of my must-see sessions.
Also among the top talks in my book is a keynote from Thomas H. Lee of Stanford on “The First Transatlantic Cable and the Birth of Engineering.” I put this one in my just-for-fun category.
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