Startup Invionics says its custom EDA tools can be used to differentiate existing design and verification flows to speed the development process and/or producing higher-performance, lower-power devices.
A 30,000-foot view of the standard semiconductor (ASIC, ASSP, SoC) development process includes creating functional blocks along with their associated testbenches, and then assembling these blocks -- along with third-party IP blocks -- into the full chip along with its associated testbenches. The main development flow includes staples such as simulation, synthesis, and place-and-route.
In some cases, designs start at an even higher level of abstraction -- e.g., C/C++ coupled with high-level synthesis (HLS) -- but with these output RTL (register-transfer level) representations in Verilog or VHDL. These RTL representations are subsequently handed from tool-to-tool as the design proceeds throughout the flow.
There are, of course, many other point-tools and utilities that come into play to perform tasks like RTL assembly, IP insertion, Linting, Design Rule Checking (DRC), Padring Insertion, Design for Test (DFT) insertion, and so forth. The "Big Three" EDA vendors provide default versions of many of these tools, but this limits the ability of the chip design teams to differentiate themselves.
Design teams combine commonly used third-party IP blocks with their own "secret sauce" functional blocks, where these custom blocks differentiate their products. Similarly, custom EDA tools can be used to differentiate the underlying design and verification flows, where these tools may speed development flows and/or produce high-performance, lower-power devices.
The logical way to augment existing flows is to access and modify the RTL at various stages throughout the flow. In the not-so-distant past, a huge number of small EDA startup companies appeared on the scene offering innovative point tools. As time passed, however, many of these companies were acquired by the Big Three, while the others tended to fall by the wayside.
The alternative is for the semiconductor design and verification teams to create their own "secret sauce" tools in-house, but doing this from the ground-up requires a significant amount of time (possibly several years) and resources. To address this, a new EDA startup called Invionics has introduced the Invio Platform, which allows custom EDA tools to be created in only days, weeks, or months, according to the company.
At the core of the Invio Platform is an RTL processing engine that accepts industry-standard languages and formats such as Verilog, Verilog-AMS, SystemVerilog, VHDL, and IP-XACT. By means of a Tcl or Python API, design and verification engineers can create robust, high-capacity, high-performance, custom tools and flows.
The RTL Processing Engine is augmented by a Custom GUI Builder and an Application Packager that can present the tool to the users in the form of a standalone executable. Invionics says that the use of its Invio Platform speeds in-house EDA tool development and solves critical design flow bottlenecks.
The Invio Platform is available now -- evaluation and pricing are available upon request. For more information, visit the Invionics website located at: www.invionics.com.
— Max Maxfield, Editor of All Things Fun & Interesting